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Published on Mar 22, 2016
Software defined radios can be implemented on general purpose processors like a PC, if the required processing power is low (e.g. if the processed bandwidth is low). A processor offers a high flexibility: It can not only be used to process the data samples, but also to control receiver functions, display a waterfall or run demodulation software. However, if high processing power is required (such as for high bandwidths) processors often do not provide enough processing power. Then the SDR algorithms have to be implemented as custom designed digital circuits on a FPGA (field programmable gate array) microchip. A FPGA provides a very high processing speed, but also lacks flexibility. The circuits is designed for one specific task only and usually it is very difficult to run software on a FPGA. Recently the FPGA manufacturer Xilinx has introduced a hybrid SoC (System on Chip), that combines both approaches. It features a dual ARM Cortex A-9 processor and a FPGA, thus combining the flexibility of a processor with the processing power of a FPGA on a single chip. The Zynq is therefore very interesting for use in SDRs. A widely used development board for the Zynq is the Zedboard (www.zedboard.org). It adds 512 MB DDR3 RAM, an audio codec, HDMI and VGA interface, general purpose IO pins, an FMC connector for daughter boards, USB and Ethernet. A Linux system can be run on the board, making it a standalone embedded computer system, if keyboard, mouse and monitor are connected. In this paper the features of the Zynq SoC and the Zedboard for SDRs will be presented. As an example a direct sampling receiver has been implemented on the Zedboard using a high- speed 16 bit ADC with 250 Msps.