 Hello and welcome to this presentation of the ARM Cortex-M0 Plus Core, which is embedded in all products of the STM32WB microcontroller family. STM32WB microcontrollers integrate an ARM Cortex-M0 Plus Core in order to benefit from the incomparable performance per milliwatt ratio. All Cortex-M CPUs have a 32-bit architecture. The Cortex-M3 was the first Cortex-M CPU released by ARM. Then ARM decided to distinguish two product lines, high performance and low power, while maintaining the compatibility between them. The Cortex-M0 Plus belongs to the low power product line. It is designed for battery-powered devices, very sensitive to power consumption. The Cortex-M0 Plus Core delivers more performance than the Cortex-M0 Core, thanks to the two-stage instruction pipeline. Let's start our description of the CPU by the processor core in charge of fetching and executing instructions. Most V6M instructions are 16-bits long. There are only 6 32-bit instructions, and most of them are control instructions rarely used. However, the branch and link instruction, which is used to call a sub-program, is also 32-bits long in order to support a large offset between this instruction and the label pointing to the next instruction to be executed. Ideally, 1 32-bit access for every two 16-bit instructions results in less fetches per instruction. During clock number two, no instruction fetch occurs. The AHB light port is available to execute a data access when instruction N is a load store instruction. On a given branch, fewer prefetched instructions are wasted, thanks to the two-stage pipeline. In clock number one, the processor fetches INST0 and an unconditional branch instruction. In clock number two, it executes INST0. In clock number three, it executes the branch instruction while fetching the two next sequential instructions, INST1 and INST2, called branch shadow instructions. In clock number four, the processor discards INST1 and INST2 and fetches INSTN and INSTN plus 1. The Cortex M0, M3, and M4 implement a three-stage pipeline, fetch, decode, and execute. The number of branch shadow instructions is larger, up to four 16-bit instructions. The Cortex M0 Plus has neither a cache nor internal RAM. Consequently, any instruction fetch transaction is steered to the AHB light interface, and any data access is steered to the AHB light interface. Note that the STM32WB implements an SOC-level cache, external to the CPU. The AHB light masterport is connected to a bus matrix, enabling the CPU to access memories and peripherals. Since transactions are pipelined on AHB light, the best throughput is 32 bits of data or instructions per clock with a minimum two-clock latency. For more details, please refer to these application notes and the Cortex M0 Plus programming manual available on the www.st.com website. Also, visit the ARM website, where you will find more information about the Cortex M0 Plus Core.