Anirudh Devgan, sr. vice president of Cadence's Digital & Signoff Group, shares the news about the company's new digital design implementation tool. With Innovus™ Implementation System, engineers can meet their power, performance, and area (PPA) and turnaround time (TAT) targets without any tradeoffs. The tool, with its massively parallel architecture, is ideal for designs at advanced 16/14/10nm FinFET processes as well as established processes.
Whiteboard Wednesdays is a video blog series that will shed some light and provide some practical insights on how to address a variety of intellectual property (IP) related design challenges. We hope you find this series to be helpful. We also welcome your feedback. Share your ideas for future episodes and any other comments or questions in the Comments area under this blog post.