The SDAccel™ development environment for OpenCL™, C, and C++, enables up to 25X better performance/watt for data center application acceleration leveraging FPGAs. SDAccel, member of the SDx™ family, combines the industry’s first architecturally optimizing compiler supporting any combination of OpenCL, C, and C++ kernels, along with libraries, development boards and the first complete CPU/GPU like development and run-time experience for FPGAs.
Short "How To" videos on utilizing the Xilinx Vivado Design Suite
Accelerating the development of smarter systems requires levels of automation that go beyond RTL level design. With the introduction of the Vivado™ Design Suite, Xilinx delivers a SoC-strength, IP-and system centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation
This collection of Xilinx UltraScale architecture training videos is designed to quickly familiarize you with the UltraScale architecture and how to use the new capabilities in the Vivado Design Suite. There are many new and exciting features in the UltraScale architecture which, after watching these short, instructional videos, you will be able to understand to quickly start using in your own projects. For further information on the UltraScale architecture. Please visit http://www.xilinx.com/training/ultrascale/index.htm
This collection of Xilinx Zynq-7000™ All Programmable System on a Chip training videos is designed to quickly familiarize you with the Zynq-7000 devices and the extensive ecosystem of development tools, OS/RTOS, development platforms and peripherals/accelerators available. When you are ready, take your new found knowledge to the next step by signing up for hands-on training with the Zynq-7000 family.