Hear Paul Cunningham, VP of R&D at Cadence, explain how the company's new Modus™ Test Solution reduces test time for digital logic by up to 3X compared to other available solutions—without impacting chip size or yield. After watching the video, learn more about the Modus Test Solution here: http://bit.ly/1Skbda1
Whiteboard Wednesdays is a video blog series that will shed some light and provide some practical insights on how to address a variety of intellectual property (IP) related design challenges. We hope you find this series to be helpful. We also welcome your feedback. Share your ideas for future episodes and any other comments or questions in the Comments area under this blog post.