 Hello, and welcome to this presentation of the Reset and Clock Controller, or RCC, for STM32H7, X3, X5, and X7 microcontrollers. The RCC is linked to the Power Controller Block, or PWR. Before going through this slide set, please have a look at the slides concerning the PWR block. The STM32H7, X3, X5, X7 Reset and Clock Controller manages the reset, the system, and peripheral clocks generation. STM32H7, X3, X5, and X7 devices embed four internal oscillators, two oscillators for an external crystal or resonator, and three phase-locked loops, or PLLs. Many peripherals have their own clock, independent of the system clock. The STM32H7, X3, X5, and X7 RCC provides high flexibility in the choice of clock sources, which allows the system designer to meet both power consumption and accuracy requirements. The numerous independent peripheral clocks allow a designer to adjust the system power consumption without impacting the communication baud rates, and also to keep certain peripherals active in low power mode. Safe and flexible reset management without any need for external components reduces application costs. The RCC manages several types of resets, the power reset, the system reset, D1 and D2 domain reset, the local resets, and the backup domain reset. Thanks to the voltage monitoring function included in the PWR block, the filters embedded in the NRST pad and the RCC reset control, the amount of external components is reduced to a single external capacitor connected on the NRST pin. The first type of reset is the system reset, which resets all the registers except certain registers for the reset and clock controller and power controller. It also does not reset the backup domain. Many sources can generate a system reset. An invalid voltage on the VDD or VCOR supply, CPWR block for details. An invalid function on VDD due to the brownout function. The brownout function allows the user to choose their own threshold levels for the VDD supply, CPWR block for details. An exit from standby mode, a low level on the NRST pad, a timeout from one of the independent watchdogs or IWDG 2-1, a timeout from one of the window watchdogs if allowed by the reset scope bits, WW2-1 RSC. Software reset request initiated by the Cortex M7 named CPU-1 or Cortex M4 named CPU-2. A low power mode security reset, which is generated when stop or standby mode is entered, but is prohibited by the option byte configuration. Note as well that a system reset asserts the NRST pad, which can be used to reset external components on the board. The reset source flag can be found in the RCC control and status register. The power-on reset is generated when the VDD or VCOR voltages are lower than a certain voltage threshold. The backup domain reset occurs when the BD-RST bit in the RCC-BDCR register is set to 1 by the application, as shown in the figure. When the VDD and VBAT are powered on if both supplies have previously been powered off. A D1 or D2 domain reset occurs when one of the two domains has been switched off. In addition, the peripherals have individual reset control bits. It is also possible to reset the CPU-1 and its associated window watchdog WWDG1 or RSTC1 and to reset the CPU-2 and its associated window watchdog WWDG2 or RSTC2. The power-on reset is the reset having the largest coverage. The power-on reset resets all the logic located in the VDD and VCOR domains, except those in the backup domain powered by VBAT, which contains the RTC and the external low-speed oscillator. Note that the power-on reset also triggers the system reset, so the NRST pad is asserted during a power-on reset. The system reset resets most of the logic located in the VDD and VCOR domains, except certain resources located in the RCC and PWR blocks. The backup domain is not affected by this reset. The backup domain reset resets the backup domain powered by VBAT, which contains the RTC and the external low-speed oscillator. The domain reset resets the complete D1 and D2 domains when the corresponding power switch is activated. The hold-boot function can be used to set one of the two processors to hold after a system reset or an exit from standby mode. This function can be useful if one processor has to boot in advance, for example, to perform the system initialization. Note that when one of the processors is in hold, it does not prevent the system from entering standby mode. The RCC offers a large choice of clock sources, which can be selected depending on low power, accuracy, and performance requirements. STM32H7X3X5 and X7 device embeds four internal RC oscillators. A high-speed internal RC oscillator, or HSI, which can work at 64, 32, 16, or 8 MHz. A low-power internal RC oscillator, or CSI, working at 4 MHz. An accurate RC oscillator working at 48 MHz. And a low-speed internal 32 KHz RC oscillator, or LSI. STM32H7X3X5 and X7 devices embed two oscillators for use with an external crystal or resonator. A high-speed external 4-48 MHz oscillator, or HSE, with a clock security system. And a low-speed external 32.768 KHz oscillator, or LSE, also with a clock security system. The STM32H7X3X5 and X7 device also embeds three phase-locked loops, each with three independent outputs for clocking different peripherals at different frequencies. The high-speed internal oscillator, or HSI, is a 64 MHz RC oscillator, which provides fast wake-up times. The HSI is trimmed during production testing, and can also be user-trimmed. A dedicated divider can generate a 32, 16, or 8 MHz clock. The HSI can be selected as a clock at wake-up from system stop. And as the backup clock if an HSE failure is detected by the clock security system. The HSI can remain powered when the system goes to stop mode in order to speed up the wake-up time. Certain peripherals, such as the I2C's and USART-LPUART, can request the activation of the HSI in system stop mode in order to generate wake-up events. The HSI is enabled by the peripheral only for the wake-up sequence detection, and remains disabled outside of this wake-up sequence. The low-power internal oscillator, or CSI, is a 4 MHz RC oscillator, which provides fast wake-up times. The CSI is trimmed during production testing, and can also be user-trimmed. The CSI can be selected as a clock at wake-up from system stop. The CSI can remain powered when the system goes to stop mode in order to speed up the wake-up time. Certain peripherals, such as the I2C's and USART-LPUART, can request activation of the CSI in system stop mode in order to generate wake-up events. The CSI is enabled by the peripheral only for the wake-up sequence detection, and remains disabled outside of this wake-up sequence. The high-speed external oscillator, or HSE, provides a safe crystal oscillator system clock. The HSE supports a 4 to 48 MHz external crystal or ceramic resonator, and also an external source in bypass mode. A clock security system automatically detects an HSE failure. When detected, a non-mascable interrupt is generated, and a break input can be sent to timers in order to put critical applications such as motor control in a safe state. When an HSE failure is detected, the system clock is automatically switched to HSI, so the application software does not stop in case of a crystal oscillator failure. STM32H7X3X5 and X7 devices embed an ultra-low-power 32 kHz RC oscillator, or LSI, which is available in all modes except VBAT mode. The LSI can be used to clock the RTC, UARTs, the low-power timers, and the independent watchdogs. The accuracy of the LSI is plus or minus 1.8%. The LSI consumption is typically 130 nanoamps. The 32.768 kHz low-speed external oscillator, or LSE, can be used with an external crystal oscillator, or resonator, or with an external clock source in bypass mode. The oscillator driving capability is programmable. Four modes are available, from ultra-low-power mode with a consumption of only 290 nanoamps to high-driving mode. A clock security system monitors the failure of the LSE oscillator. In case of failure, the application can switch from the RTC clock to the LSI clock. The clock security system is functional in all modes except VBAT mode. It is also functional under reset. The LSE can be used to clock the RTC, the use-arts, or low-power UART peripherals, and the low-power timers. The PLLs embedded in STM32H7X3X5 and X7 devices provides a flexible way to generate the required frequency for the system or peripheral clocks. They offer a wide input frequency range from 1 to 16 MHz. If the input frequency is between 1 and 2 MHz, then the user has to select the VCOL path. If the input frequency is between 2 and 16 MHz, then the user has to select the VCOH path. The two VCOs also have a smart frequency range, 150 to 420 MHz for VCOL and 192 to 836 MHz for VCOH. The PLLs also provide three different outputs, which are all derived from the VCO output via post dividers, DIVP, DIVQ, and DIVR. In addition, it is possible to change the values of the post divider without disabling the PLLs. The application just needs to disable the corresponding post divider, change the division ratio, and re-enable the post divider. In order to get a duty cycle close to 50%, the application has to program the post dividers to even values. In addition, the PLLs can be switched to fractional mode, allowing a high precision in the VCO frequency. The 13-bit fractional divider can be changed without disabling the PLLs. This feature can be used to perform accurate clock drift compensation. The PLLs share the same clock source, HSI, CSI, or HSE. Each PLL has a dedicated pre-divider in order to adjust the reference clock for each PLL. PLL 2 and PLL 3 are dedicated to the generation of the kernel clocks for the peripherals. Certain peripherals, such as the SAI, USB, etc., may require a specific frequency. The PLL 1P output is used as system clock for processors and buses. The PLL 1R is dedicated for the debug trace, and the PLL 1Q is also used as kernel clock for peripherals. Note that the PLL's clock source cannot be changed if one of the PLLs is enabled. The system clock can be derived from the HSI, CSI, HSE, or the output of DIVP of PLL 1. The switch used to select the system clock is dynamic, meaning that it is possible to change the frequency on the fly without generating timing violations. In addition, all the pre-scalers presented in the figure are dynamic, so they can be changed on the fly as well, making the frequency scaling operation very simple. The clock of the CPU 1 does not exceed 480 MHz. The AHB clocks do not exceed 240 MHz, as well as the CPU 2 speed. The APB clocks do not exceed 120 MHz. Note that HR TIM and certain timers can use clock frequencies up to 480 MHz. The clock for the RTC AWU can be selected from among LSE, LSI, or HSE divided. Note that when HSE divided is used as a kernel clock for the RTC AWU, the frequency cannot exceed 1 MHz. Note as well that if LSI is used as a kernel clock for the RTC AWU, the RTC AWU will no longer be clocked if the VDD and V-Core supply are removed. If HSE divided is used as a kernel clock for the RTC AWU, the RTC AWU will no longer be clocked if the system goes to stop mode or if the V-Core supply is removed. The LSE can remain enabled in all low power modes and in V-Bat mode. The RCC also provides two clock output signals, MC01 and MC02. A pre-scaler allows the application to adapt the frequency to the pad's capability. Many STM32H7, X3, X5 and X7 peripherals have different clocks for the data and control streams via the processor bus interface, as well as the clock for the specific peripheral interface. Generally, the clocks for the data and control streams via the processor bus interface are named bus clocks, and the clocks for the peripheral specific interface are named kernel clocks. The peripheral clocks represent the clocks received by the peripheral, bus clocks and kernel clocks. Having a separate bus clock and kernel clock allows the application to change the interconnect and processor working frequency without affecting the peripheral. For certain peripherals, it is also possible to disable the bus clock as long as the peripheral does not need to transfer data to the system. So, it gives a good flexibility on the frequency selection for the bus processor and memories and the real need of the peripheral interface. For example, the UARTs have a kernel clock which is used, among other things, by the baud rate generator for the serial interface communication and an APB clock for the register interface. In addition, certain peripherals are able to request the kernel clock when they detect specific events. The distribution of the kernel clocks is not detailed in this presentation. Please refer to the reference manual for specific details. Most of the peripherals receiving a kernel clock have a dynamic clock switch to select the optimal clock source. The proposed clock sources generally come from one of the seven PLL outputs dedicated to the kernel clock generation. Internal or external oscillators. This is mandatory for peripherals needing a kernel clock when the system is in stop mode. Pads, for example, on peripherals using an external PHY, but also for audio as well, in order to use a clock reference from an external device. And other internal peripherals for synchronization between blocks. The dynamic switching facilitates the transition from one source to another. RCC registers are used to configure the kernel clocks for all the peripherals. Peripherals generally receive one or several bus clocks and one or several kernel clocks. Each processor can control the clock gating of the peripheral clocks via dedicated registers located in the RCC. The gating of the peripheral clocks depends on several parameters. The clock-enabled bits. Each processor has a dedicated control bit for that, named C1, PERXEN, and C2, PERXEN for simplification. The low-power clock-enabled bits. The processor states C-run, C-sleep, or C-stop. And the autonomous bits for peripherals located in the D3 domain. Setting the bit C1, PERXEN to 1 indicates that the peripheral PERX is enabled for the CPU-1. Setting the bit C2, PERXEN to 1 indicates that the peripheral PERX is enabled for CPU-2. This operation is named allocating a peripheral. It is important to note that the RCC offers two register sets, allowing each processor to enable or allocate peripherals. The peripheral allocation informs the RCC that the CPU-1 or CPU-2 are enabled by a peripheral. This information is used by the RCC for the clock control in low-power modes. So before using a peripheral, the CPUs have to allocate it. The same peripheral can be allocated by both processors. It is up to the application to avoid resource conflicts. Certain peripherals are implicitly allocated to a specific processor. The flash, access RAM, ITCM, DTCM-1 and DTCM-2 are implicitly allocated or enabled for CPU-1. CPU-2 can allocate any of them, but by default they are not allocated to CPU-2. The D2 SRAM-1, D2 SRAM-2 and D2 SRAM-3 are implicitly allocated or enabled for CPU-2. CPU-1 can allocate any of them, but by default they are not allocated to CPU-1. Certain other peripherals are allocated to both processors. This is the case for IWDG-1, IWDG-2, RCC, PWR, EXTI and D3 SRAM-4. When a CPU allocates a peripheral, this peripheral is linked to the processor state for the low-power modes. The CPU plus the peripherals allocated by this CPU and the associated interconnect is considered by the RCC as a CPU subsystem. The D1 and D2 domain core voltages can be switched off. To give a simple example of how the RCC uses the peripheral allocation, we can state that the RCC will not allow a domain to be switched off if one of the peripherals of this domain is used by the processor of the other domain which is not switched off. The following table gives a simplified view of the system states versus domain states. A domain is in D-run mode when its bus matrix is clocked. Its bus matrix will be clocked if a CPU which is in C-run, C-sleep mode allocated a peripheral on this domain. A domain is in D-stop mode when its bus matrix is no longer clocked. The CPU of this domain is in C-stop mode. The other CPU is not allocating peripherals on this domain or the CPU is also in C-stop mode. A domain is in D-standby mode when its V-core supply is switched off. Note that it is possible to keep only the D3 domain in D-run mode while other domains are in D-standby mode. For more details on system states, please refer to the PWR training slides. Note that when the system resets, for example after a system reset, the HSI is selected as the system and peripheral clock. The CSI, HSI 48 and HSE are off as well as the PLLs. The LSI is still working if it was previously enabled. After a system stop the PLLs are switched off. The application can choose either the HSI or CSI as the system clock and peripheral clock. The HSI 48 and HSE are off. After a D1 or D2 domain exits D-stop or C-stop mode, the RCC maintains the same clock setting as the one used before going to low power mode. C-sleep mode does not affect the clock settings, but only acts on the clock gating. The autonomous mode offers the capability of providing peripheral clocks to peripherals located in D3. Even if the CPU to which they are allocated is in C-stop mode, and if both D1 and D2 domains are in D-stop or D-standby mode. The gating of the clocks of peripherals in autonomous mode depends on the mode of the D3 domain. If the D3 domain is in D-run mode, the peripheral will receive its peripheral clocks. If the D3 domain is in D-stop mode, the peripheral clocks are gated, but the peripherals can still request the kernel clock if they have this capability. The autonomous mode does not prevent the D3 domain from entering D-stop or D-standby mode. The D3 domain is able to switch alternatively from D-run to D-stop mode and then from D-stop to D-run mode according to peripheral activity. For example, if the system is expecting messages via I2C4, the complete system can be put in stop mode. When the I2C4 detects a start bit, then it will generate a kernel clock request. This request enables the HSI or CSI, and a kernel clock is provided only to the requester. Then the I2C4 can decode the incoming message. Several cases may occur. If the device address of the incoming message does not match, then the I2C4 releases its kernel clock request until a new start condition is detected. If the device address of the incoming message matches, the message has to be stored in the D3 local memory. The I2C4 is able to generate a wake-up event on a dress match in order to switch the D3 domain to D-run mode. When the D3 domain is in D-run mode, the bus interface clock is activated, allowing the I2C4 to transfer the message into memory via DMA1. If the D3 local memory is not full, then the D3 domain will go back to D-stop mode without any CPU activation. If the D3 local memory is full, the DMA1 can generate a wake-up event in order to activate CPU1 or CPU2. Please refer to the D3 domain low power slide set for details. Certain peripherals such as the UARTs and I2Cs are able to asynchronously detect events requesting a kernel clock for the processing. The RCC can provide on-demand a kernel clock to those peripherals. With a CPU allocating the peripheral is in C-stop mode or if the system is in stop mode. The kernel clock request will work if the selected kernel clock is HSI or CSI. In order to speed up the activation time, the HSI or CSI can be maintained activated during system stop mode. In system stop mode, the LSI and LSE clocks are still available for peripherals. A kernel clock is provided to the peripherals located in D1 or D2 domains if one of the following conditions is met. When the CPU to which the peripheral is allocated is in C-run mode and if its enable bit is set to 1. 2. When the CPU to which the peripheral is allocated is in C-sleep mode and if its LP-enable bit is set to 1. 3. When the CPU to which the peripheral is allocated is in C-stop mode and if its LP-enabled bit is set to 1 and the peripheral is generating a kernel clock request and the kernel clock source is HSI or CSI. And 4, when the CPU to which the peripheral is allocated is in C stop mode and if its LP-enabled bit is set to 1 and the kernel clock source is LSE or LSI. The bus interface clock will be provided to the peripherals only when conditions 1 or 2 are met. A kernel clock is provided to the peripherals PERX of the D3 domain if one of the following conditions is met. 1. When the CPU to which the peripheral is allocated is in C run mode and if its enable bit is set to 1. 2. When the CPU to which the peripheral is allocated is in C sleep mode and PERX LPEN equals 1. 3. When the CPU to which the peripheral is allocated is in C stop mode and the D3 domain is in D run and if its LP enable bit is set to 1. 4. When the CPU to which the peripheral is allocated is in C stop mode and the D3 domain is in D stop and if its LP enable bit is set to 1 and the peripheral is generating a kernel clock request and the kernel clock source is HSI or LSI. Or 5. When the CPU to which the peripheral is allocated is in C stop mode and the D3 domain is in D stop mode and if its LP enable bit is set to 1. Of the peripheral is LSE or LSI. The bus interface clock will be provided to the peripherals only when conditions 1 2 or 3 are met. This slide list the RCC interrupts the LSE and HSE clock security systems the PLL ready and all six oscillator ready signals can generate and interrupt. In addition to this training you may find the power control and interrupt controller training is useful.