 Welcome to class 28 of topics in power electronics and distributed generation. We have been looking at the common mode and differential mode analysis of power converter and the differential mode signals are quite important because they are primarily responsible for power transfer. So, the basic purpose for operating the power converter is power transfer. So, the study of the differential mode operation of it is important part. The common mode signals are important when you are looking at other perspectives such as circulating possibility for circulating currents in the converter possibility or the EMI characteristics EMI perspective of the power converter. The other thing we saw in the last class is that the common mode and differential mode analysis can be performed on a on using both the switching model and the averaging model average model and if you look at a single phase inverter. So, this is a single phase two leg converter earlier we had looked at a single phase center tap capacitor converter. So, you could look at it from the common mode and differential mode analysis and look at what how the these circuits would behave. In particular for the two leg converter we looked at a modulation method where you are switching both legs of the power converter because now you have two legs there are a lot of possibilities for the way in which you could now have PWM on the two legs. The method that we looked at the modulation method one where we had the duty cycle for leg A and duty cycle for leg B to be symmetric around 0.5 and if you look at the DA and DB essentially they are symmetric around 0.5 and the characteristics that we saw is effectively the output frequency is doubled. So, you have two pulses coming in the output for during every switching period you also have the polarity of the output pulses being in the polarity of the commanded voltage that you would like. So, we called as unipolar modulation if you have pulses of both polarity coming during the operation that would be a bipolar modulation. We look at a couple of other possibilities for the way in which you could modulate the power converter here both legs are switching. One possible method for modulating the power converter could be that you could switch say leg A at high frequencies when you want to get a positive output voltage you could say you could you could turn on say this particular device. So, if this particular device is on leg B would be connected to the negative DC bus. So, using VDC you could synthesize a positive voltage. If you want to synthesize a negative voltage you could turn on this particular leg and switch the leg A. So, because now leg B is connected to positive you have minus VDC and by appropriately switching leg A you could synthesize a negative polarity output voltage. So, you could do this by considering signals. So, we will consider a modulation method too. So, if your leg B is modulated at the fundamental frequency which is 50 hertz in our case and if our desired output voltage has was of the form A V cos omega t then essentially what we would have is D B could be a signal which would be 0 if V o star is positive and 1 if V o star is negative. So, if you look at the switching signals the switching functions for leg B your S B plus would be a signal of the form 1 if V o star is less than 0 and 0 otherwise. So, essentially your leg B is switching at fundamental frequency and leg A is switching at the carrier frequency. So, if you look at the duty cycle signals that are being applied for leg A we have D A is equal to and 1 plus A V by V DC cos omega t otherwise. Again your leg B the D B was going between 0 and plus 1 with not taking any values in between whereas now D A is having a value which goes between depending on the polarity of your output voltage that you would like to synthesize it takes on signals. So, because your D A is now a continuous a signal between 0 and 1 your S A plus switching function transitions occur at FSW. If you look at V A B on a differential mode essentially the output signals will have if you look at your D B D B is now switching at the fundamental frequency. So, this is time in milliseconds. So, it is so 1 fundamental frequency would correspond to a duration of 20 milliseconds D A what we had written the expression would now have a form which looks like this red dotted line and the height of this particular D A signal would depend on the amplitude of your AC signal that you are trying to synthesize. So, if you then zoom in to some region of your PWM operation say in this particular between 15 and say 20 milliseconds you would have waveforms that look like this S B plus is now just staying low your S A plus would now be switching between 0 and plus 1 depending on the amplitude of this D A signal and you can see that your effective output frequency is now FSW. So, you lose the advantage of 2 FSW that you had in the previous modulation case you have now your effective output switching frequency which is at FSW rather than 2 FSW. If you so if you can actually write an expression for V differential mode of your output is V DC into S A plus minus S B plus. So, you can see that despite the slightly more complex shape of S A plus and S B plus your effective output voltage would be the desired sinusoid. If you look at your common mode signals that we had we wrote an expression for V common mode of your input which was V DC into half minus S B plus. So, you can see that now because your S B plus has a shape it is 0 in the regions say 0 to 5 seconds it would be high between 5 and 15 your S B plus function is now switching at the fundamental frequency. So, if you look at your common mode signal that is coming in your output you are jumping between plus V DC by 2 and minus V DC by 2 at your fundamental frequency which is much lower than your switching frequency which means that your high frequency transitions which would cause spikes of current to flow into the ground is occurring at a much lower repetition rate. So, your expected problems of EMI with this particular modulation method could be lower than with the modulation method one that we previously saw discussed. So, it could be easier to build a EMI filter. So, the EMI issues is not just about the topology it is also related to how you are actually conducting the switching operations. So, if you now look at the option that we had looked at we were switching leg B at the fundamental frequency and we switched leg A at high frequency. We could also do take a different alternative approach where we switch leg B at the switching frequency and we could switch leg A at the fundamental frequency. So, we will call that modulation method 3 where da is 1 if vo star is positive. So, this would correspond to SA plus being equal to 1 and 0 otherwise and your db for the other leg would be 1 minus av by v dc cos omega t if vo star positive or minus av. Again you can see because your vo output voltage is v dc into da minus db you get the same differential mode output signal in all the three modulation methods. So, the differential mode signals would not change if you look at the shape of the waveforms in the modulation method 3 you can see that now da is now switching at the fundamental frequency and db is now having a value which lies in between 0 and plus 1 which means that db will be switching at higher frequencies. So, SB plus is the one which is switching and SA plus is now staying at 0. So, if you are looking at may be a zoomed in region around there it would correspond to waveforms that has been drawn below. If you look at your common mode signal in this particular case we can we have vcm of your input is v dc into half minus SB plus in this case we can see that your input would see high frequency on the common mode. So, we have problems with the high frequency on your input side you also have now only fsw as your output equivalent switching frequency which means that we lost the advantage of 2 fsw. So, we can see that this so your differential mode signals v dm out is still the same v dc into SA plus minus SB plus. So, your output switching frequency is still at fsw. So, modulation method 3 is poor from both the input and output perspective. So, you by not being careful about which leg you are switching at the appropriate rate you could end up with exacerbating the problems that you are facing in your power converter without getting any advantage either at the input or at the output. So, one thing that also to keep in mind is that we were looking at it at the operation of this power converter from the input and output voltage waveform basis. Another important factor to keep in mind is how these legs of the power converter would operate on a thermal basis if you are switching say one leg at fsw at the carrier frequency and the other leg at fundamental frequency it means that one leg is having higher losses and the other leg is having lower losses. So, from a thermal loading perspective the temperature rise on one leg would be more and the compared to the other leg. So, if you are using a H bridge module you may not be fully utilizing your semiconductors. So, you will have to look at all the factors in mind depend to look at what are the advantages and disadvantages of one particular topology or one particular method of operating your switches in a power converter. So, now that we have looked at this two leg power converter we could ask a similar question as we did for our center tapped capacitor topology of what would be the design issues behind the DC bus capacitor for this particular topology how does it compare with the center tapped capacitor topology. So, we will look at this design with the same example as what we looked at in for a center tapped capacitor. So, we will consider a 2 kilowatt 230 volt unity power factor power converter, but now with a single phase two leg inverter topology modulating with method one ok. And we will assume that your switching frequency is 10 kilohertz your carrier frequency is 10 kilohertz. So, your effective switching frequency is seen by your filters would be at 20 kilohertz. The ambient temperature and the operation of the power converter is kept the same. So, we know that from our average model for the power converter VAB is dA minus dB times VDC and dA is half plus m cos omega t by 2 dB is again symmetric about the 0.5 point. So, VAB can be written as m VDC cos omega t and if we are trying to synthesize a 230 volt AC output you are talking about VDC of the order of 325 volt for V o this 230 volts RMS. Again we have to consider factors such as the grid voltage variation, dead band on state drops in the devices etcetera. So, we will consider 5 percent for VAC variation and dead band effects and 10 percent drop for filtered. So, the actual DC bus voltage that we might need to use would be higher. So, it would be of the order of 400 volts rather than 325 volts with ideally. So, again for the selection of the capacitors we are talking about capacitors which are rated at 4 higher than 400 volts may be 450 volts would be a suitable choice. So, we will consider we will. So, for our analysis we could do a similar analysis for the power converter. We could match the power flow between the input and output of the power converter. So, if we take a single leg converter we looked at your P out and we looked at the power flow N to evaluate the DC current and the 100 hertz ripple that would be seen by the DC bus capacitors. We could do a similar analysis to evaluate what would be the 100 hertz ripple on the DC bus. So, we have V DC times I P of T which is the positive DC bus current we will call it I DC P. So, we know the AC voltage is 230 volts we know the power is 2 kilowatts. So, we know what our A I is. So, you could calculate I DC P. So, this DC current that flows through at which has a value of A V A I by 2 V DC and there is a 100 hertz component that is flowing through which would have a RMS value of A V A I by 2 root 2 V DC. So, the next component that we would like to evaluate for this particular power converter is due to the switching operation what is the high frequency components that now flow through the DC bus capacitor and you could evaluate the high frequency components by looking again at the switching functions. So, if you have SA plus to have a shape such as this and SB plus to have a shape such as this and you have your I out when SA plus is wider than SB plus then this particular point this region in between the width of this region would be equal to dA times T s and the width of this particular duration is dB times T SW T SW and then you could calculate what is the average of this particular DC bus positive current and what is the RMS value your average current would then be equal to is I out to dA minus dB again depending on the polarity of I out it could be positive or negative your RMS quantity on a per switching cycle basis would be magnitude of I out into square root of the magnitude of dA minus dB. So, again this is this gives the RMS value on per switching duration per T SW you could then sum it over all the switching durations and one fundamental cycle to calculate your high frequency RMS currents for a switching frequency of 10 kilohertz and your T SW is 100 microseconds and your fundamental frequency is 50 hertz. So, we have number of points per fundamental is 20 milliseconds by this 100 microseconds so that would give you 200 points. So, your high frequency current so this is I out of N T s the whole thing under square root will give you your RMS currents. So, essentially you are summing up the RMS over all the switching T SW s. So, we could then ask a similar question as what we did for our DC bus capacitor midpoint topology of what is the RMS currents what would be the voltage ripple what would be the power dissipation temperature rise the number of capacitors you need to place in parallel and we could then for the particular this particular example will consider the same capacitor as what we considered for the previous topology. So, we will assume a 450 volt 150 micro farad capacitor with the given ESR of 0.8 ohms at 100 kilohertz. We will assume the data to be is the same as what we had the previous time. We will assume that the high frequency current multiplier is 1.4 RMS even at 20 kilohertz we had taken 1.4 RMS at 10 kilohertz we will assume that it stays flat even at 20 kilohertz. And the data is same as what we considered for the DC bus capacitor midpoint topology. So, essentially the current multipliers as we saw gives information about the ESR of the capacitor as a function of frequency. So, if in this particular topology we know that it is 0.8 ohms ESR at 100 hertz and your current at 100 hertz is 1 amp. So, I square R is 1 square into 0.8. So, the ESR at 20 kilohertz into 1.4 amp square one would be able to calculate the ESR which. So, this turns out to have a value of 0.41 ohms. So, for this particular power converter it is 2 kilo watts 230 volts. So, your current rating IAC is 2 kilo watts 230 volts. So, this corresponds to 8.7 amps RMS or 12.3 amps peak. In this topology because the output is not connected to the capacitor through any midpoints there will be no 50 hertz component. So, the low frequency component is the 100 hertz component. So, your IDCP of t is now 1 by 400 which is your DC bus voltage into 230 root 2 cos omega t into 12.3 which is the current cos omega t assuming unity power factor of operation. So, your IDCP IDC average DC current is 5 amps and your IDC p at 100 hertz is 5 amps peak which would correspond to 3.54 amps RMS. So, to evaluate your high frequency component of the current we will we can calculate it in a similar manner as what we have just discussed. We know our I out of at NTSW is 12.3 cos and we are using modulation method 1. So, DA of NTS is 0.5 plus your output voltage is having a peak value of 230 root 2. So, this is 325. So, you have your duty cycles and your currents based on which you could now calculate what is your high frequency current flowing in your DC bus and that current now would be 2 pulses per TSW. So, you are having your DC bus current also now at 20 kilohertz and its side bands and harmonics. So, based on the expression that we had just written previously you could calculate your ICDC at 20 kilohertz is 3.83 amps. So, if you look at your total RMS current flowing through the capacitor it would now be your 100 hertz component plus your 20 kilohertz component. So, you have about 5.2 amps flowing through the DC bus capacitor and this so a single capacitor would obviously not be sufficient and we would have to connect multiple capacitors in parallel. So, if you look at the ESR numbers the ESR at 100 hertz and at 20 kilohertz is 0.41 ohms and based on the calculations from our previous example we saw that the cap capacitor which was specified for 3000 hours of life would correspond to a core temperature T core of 94.8 degree centigrade and it had a thermal impedance from core to ambient of 12.3 degree centigrade per watt. So, this is from the previous example. So, using this ESR numbers we could calculate what is the effective 100 hertz current that is flowing through the capacitor. So, effective 100 hertz current so 3.54 is the 100 hertz ripple plus 3.83 is the switching frequency ripple. So, your I 100 is 4.47 amps. So, from a thermal perspective we had seen again from the data sheet that if we have about 2 amps per capacitor and it is operating at an ambient of 55 degree centigrade you can expect about 3000 hours of life. So, if we can make use of this number by taking the 2 amps per capacitor as a design guideline we would need we need. So, we are talking about roughly 3 capacitors. So, last time we did an in the previous example an analysis with both 3 and 4 capacitors we will consider say for 4 capacitors in this case as being used in the design. So, select 4 capacitors. So, if we could then calculate the power loss per capacitor. So, this is 0.8 into so it is about 1 watt loss per capacitor. So, 4 capacitors in parallel we are talking about 4 watts loss in the bank. Your core temperature for the capacitor is 50 into 50 plus 50 is the ambient within the cabinet plus 1 watt loss per capacitor into 12.3 which is a thermal impedance degrees per watt. So, you have a core temperature of 62.3 degree centigrade and again assuming the simple thermal lifetime model you are considering 3000 into. So, you are talking about 9.8 years compared to about 4 and a half years for the other in the previous example. We could also calculate the voltage ripple. So, your capacitor bank is 4 capacitors in parallel 150 microfarads. So, this is 600 microfarads. So, your 100 hertz ripple is so you have about 13.3 volts as your 100 hertz ripple and then you could look at what is the ripple at 20 kilohertz. So, we had 3.83 amps again we will assume that this it is actually square pulses, but assuming it is a sinusoid you will have 3.83 times root 2. These are all simplifications to get an estimate of what the ripple is. So, it is about 70 millivolts. So, it is almost negligible the ripple at 20 kilohertz. This is a capacitive ripple. If you look at the ripple because of the ESR you are talking about 3.83 root 2 into 0.41 is the ESR at 20 kilohertz and there are 4 capacitors in parallel. So, you are talking about 0.55 volts. So, you can see at the switching frequency your capacitor bank is now acting more resistive than capacitive. So, you have the same concerns that you have had in the previous topology you need to if you have strain ductances you need you will have strain ductances and you need to put a snubber capacitors film capacitors in parallel. So, as to account for the rapid transitions that would be there in the current waveforms due to the switching of the transistors. So, we could look at then a comparison of the two leg inverted topology with the center tapped capacitor topology and if you look at the center tapped capacitor topology one thing is you need lesser semiconductor because you have only one leg whereas, in the two leg case you would have two legs. So, you have an additional leg semiconductors to consider. But one thing is the semiconductors are rated in this particular case for 1200 volts or other case the semiconductors might be rated for 600 volts. So, the voltage rating is not identical. In the center tapped case you have more capacitors that you would need in your capacitor bank. So, depending on the cost of your capacitors versus cost of a additional leg of semiconductor you would have different initial costs. In this particular case you have fewer DC bus capacitors, but it is not just the semiconductor leg you need to consider you need to also consider gate drives etcetera that you would need for the leg. If you look at the path for the current flow in the center tapped topology your current would be flowing through one semiconductor device be it a transistor or a diode then the return path is through the capacitor. So, you have losses due to the drops in those paths which could be the conduction drop and the drops in the ESR of the capacitor whereas, if you look at the losses in the case of the two leg converter you have the drops in two semiconductor devices and the capacitor. So, you will have to look at from a overall perspective whether the losses would be more in one case or the other it depends to a large extent on how much more dominant the capacitor ESR values are compared to the on state drops of semiconductor devices. However, the low voltage rating of the semiconductors mean that the semiconductor drops over here would not be identical to the semiconductor drops over in the center tapped topology. If you take a semiconductor device when you would go up in voltage rating the on state resistance will go up for a given current level. So, a 1200 volt device would have a higher R conduction compared to a 600 volt device. You can also consider the effect of say in modulation method one we saw that the effective output frequency is twice the switching frequency. So, your ripple current in the output filter would be lower because of the higher equivalent frequency which means that potentially you could look at whether there is some energy savings because of reduced ripple current in your output filter. From a reliability perspective the center tapped topology has fewer semiconductors switches and gate drives. So, if your reliability issues are more with semiconductor devices then one with fewer devices would be of advantage. Whereas the two leg inverter has fewer capacitors and the voltage rating is reduced. So, your clearance requirement etcetera is actually reduced. So, depending on again which is the item of concern you have different reliability implications of these two topologies. Also other factors performance factors we also we saw that in one case you have bipolar PWM in one case you have unipolar PWM also the switching frequency is effectively doubled in modulation method one. We also saw that in the center tapped topology you have low frequency essentially DC input common mode voltage whereas in modulation method one we saw that there is high frequency and the common mode input. So, you might need more EMI filtering. So, you could actually now on an overall system basis look at what it takes to actually do a comparison. Now, we have looked at essentially single phase two options for single phase power conversion, but we could see that even in this simple example we could do a very exhaustive analysis of what the implications of each design choice is. So, to take this further we more detailed analysis we need to actually look at what the implications are when you are looking at it closely from a semiconductor perspective and also from a AC filter design perspective which we will discuss later. Thank you.