  broker  industry                                                                                       we look at a couple of design style we call them circuit family so CMOS is one circuit family what we looked at was static CMOS static means I will go back and look at the static of the problem in order static means that the output is either driven by VDD or driven by ground at all time except when the input is switching only for a fraction of time it is transitioning otherwise at all times the output is driven either by VDD or ground that is why we call it static so we were looking at CMOS and specifically we were looking at static CMOS so now we look at a couple of logic families one we look at CEDO on CEDO NMOS logic we first look at what why do we want to go for anything else what does what are the reason how why are we compelled to look out for other logic families we look at dynamic logic again dynamic logic is a variation of CMOS only we had static CMOS now we have dynamic logic we in fact we saw one of the logic families earlier we saw past logic families in earlier lecture and we saw the advantages and disadvantages we wanted to do low area the disadvantage very big disadvantage of past logic class was the VT drop and in past we even saw how to solve the VT drop so we constructed a transition data out of it connecting CMOS and NMOS together so we have been seeing variations of CMOS but in this sector we see in detail these two logic families now what makes a circuit pass since the the the tool they can be three parameters of comparing different logic families and obviously is the area what is the concept on second is the how fast or how slow the cell is obviously we want faster and third is what is the power consumption in earlier technologies or smaller chips power consumption was not an issue but power consumption is in fact one of the most important factors now even more so when we consider that lot of devices that we use are battery powered so obviously we want something very dynamic in terms of power so here what we are looking at we are looking at is purely the timing we are not looking at we are looking at area and timing we are not we are not talking in terms of power now so the question is what makes a circuit pass how fast or how slow a circuit is depends on the current how fast does the current charge or discharge the capacitor so I is equal to C dv by dv so the propagation delay is proportional to C by I delta V by dv low capacitance makes a circuit faster because the smaller capacitance it takes less time to charge on the charge high current we will talk about that and a small swing a small swing means let's say you want the V dv supply with phase 5 volt and you want the small and the time it takes for the output to charge from 0 to 1 or 1 to 1 1 to 0 let's say that the time is something but if I reduce the swing to let's say 2 volts the time is obviously going from 0 to 1 or 1 to 0 from 2 to 0 volts is will be comparatively faster than the time logical effort is again proportional to C I we say that okay I is equal to so the propagation delay is proportional to C by I delta V logical effort itself is also proportional to C by I so if you notice the NOR gate on the right hand side here this NOR gate now this is the way NOR gate is sized typically when I compare to unity method so now a NOR gate we see let's say that is the input capacitance so A will see the capacitance of 4 C plus 1 C equal to 5 C now majority of the input capacitance are in fact even output output C 4 C plus 1 C plus 1 C 6 C the majority of the input capacitance and the output capacitance comes only from P MOS N MOS is a lesser factor A that is why we are saying that P MOS is the enemy because compared to N MOS it has high capacitance for a given now this is what main people are that what if if I take P MOS out of the equation if I want to take P MOS out capacitance of the input or of the output whatever so one of the most famous circuit family that tries to do that is called pseudo N MOS so the C MOS had because the complementary MOS which have P MOS and N MOS connected together pseudo N MOS on the other hand has P MOS which is always on so in all the technologies the N MOS processes had no P MOS so what was used was a pull-up transistor that is always on so this is a this is the variation over C MOS that the pull-up network is always on now the pull-down network can be on or can be off based on the value of the input let us see how this circuit works again this is an inverter so when V in is 0 N MOS is off this N MOS is off this N MOS is off T MOS is on and V out is 1 the difference comes when V in rises when V is between becomes 1 N MOS is on now but P MOS is pulling V out to 1 now if N MOS is very comparatively stronger than P MOS in terms of current kind of capability then V out will go to 0 now the time on the logic level the time after which V out goes to 0 here depends on the related spend of N MOS you can set the P MOS that is why we say that there is a ratio issue how do we size the transistor so this is a graph now in this circuit the width of P MOS is given to be P and we have made N MOS to be 16 now this is an inverter characteristic V out versus V in and the voltage characteristics are plotted for 3 different values P is equal to 4 4 P is equal to pulling and P is equal to pulling 4 now as we go here we see that this gate is becoming more and more few what do we want we want the characteristic to be as close to the unit C MOS inverter which is this one this side so the rule of thumb is that we make P MOS 1 by 4 effective strength of the polynomial flow now in a typical unit inverter using N MOS is 1 if N MOS is X P MOS is 2 X now we are saying that we make P MOS 1 by 4 compared to N MOS so N MOS is X P MOS we go X by 4 earlier it was 2 X now it goes X by 4 let us see the circuits so this is a typical structure of a typical structure of a pseudo N MOS you have a pull down network with implementing function F your pull up network is always one of the same the pull up network is only a P MOS which is always one so the function is the logic function is only consumed by the N MOS this is the pull down network what do we strive for in this case we strive for unit current or output to compare with the unit inverter so these are the circuits inverter N and N if you see try to see this in that with the P MOS you would see that the pull down network remains same the pull up network is replaced by a P MOS which is always on that is the only difference now how do we size them so we put some numbers here so if we talk about this inverter we say that okay the first switch N MOS we say N MOS is 4 by 2 so by the rule of thumb the P MOS should be 1 by 4 of the size so earlier it was it would not have been 8 now it is 2 by 3 so earlier and without without this being a pseudo N MOS let us say for a P MOS the P MOS would have been 8 by 3 now I would I will I will machine line that by 1 by 4 that being the rule of thumb so 8 by 3 if the 1 by 4 becomes 2 by 3 this is how we size this inverter NAN 2 NAN 0 2 again you could compare with the unit inverter so NAN 2 to make the pull down so the pull up network now will remain same so NAN and NON the pull up in fact remains 2 by 3 what we are worried about is the pull down network so going to NAN 2 we see the speed at a and b are 3 so the resistance will increase so what we do is we double the bit of each of the thumb so it becomes 4 by 3 become 8 by 3 for NON 2 we see that they are in parallel so they remain 4 by 3 because assuming only one is on a point so it remains 4 by 3 same as inverter now let us see what happens to the values of GMP going back to the last lecture G represents the logical effort which is the by definition it is the capacitance seen by the input of a gate divided by the capacitance and the input of an inverter so we saw that the inverter is the G value is 1 T is the parasitic capacitance which is again the value of the capacitance seen at the output of the gate compared to the value of the capacitance at the output of an inverter so now in this case whenever I will fill in the values and explain how to write now in the inverter the this inverter the pseudo inverse inverter is same as the regular CMOS inverter in the case A is 0 that is NMOS is off so in CMOS inverter also CMOS is on in this inverter also CMOS is on so the case of by being pull up that is GU means in the case of pull up and GD means G for the case where it is a pull down now so now GU GU and PU that is the case is where it is pull up and exactly same like CMOS so it should be very easy to calculate the value of VMP here AC this divided by 3 is nothing but we are saying that the length remains 3 so what we are we are comparing it against the unit inverter for which again the length remains 3 so in fact TMOS and NMOS are size as 1 by 3 and 2 by 3 yet it becomes 4 by 3 and 2 by 3 so for the GU so A see the input cap to be 4 by 3 so GU remains 4 by 3 so 4 by 3 GU remains 4 by 3 PU so why we will see the cap of TMOS on and NMOS 4 by 3 so it is 2 by 3 plus 4 by 3 it is 6 by 3 now let us consider the pull down case now what happens during pull down is what makes it different from the regular CMOS inverter for the case of pull down the PMOS and NMOS are both on now in this case the capacitance seen by both input and output are reduced now in the earlier inverter in the CMOS inverter A sees the cap of both NMOS and PMOS but here A is just seen the cap of NMOS so now we say that so in both GU and PU cases the capacitance gets further divided by 3 so whatever is the value of GU it will be the value of GU divided by 3 so 4 by 3 becomes 4 by 9 similarly PU 6 by 3 becomes 6 by 9 in fact this is what our aim was our aim was to reduce the capacitance on output and inputs by replacing the pull down network with an all in one PMOS the average value is simply GU the average is simply GU plus will be divided by 2 similarly now for 90 you could do that AMB both see 8 by 3 so GU becomes 8 by 3 GD becomes the value of GU divided by 3 similarly viruses 2 plus 8 by 3 which is 10 by 3 PD becomes 10 by 3 again further divided by 3 you could also do this similar exercise for model so we see that the value of GN by the value of GNP we see that the average value of GNP is lower than compared to a corresponding PMOS factor in fact the area is also lower you notice that the whole pull up network let us say for an N input NAND gate there will be N PMOS but here there is only one PMOS so then why is it not popular that is the question right it has lower area it has lower capacitance so it could be faster than a regular PMOS but then why is it not popular the most pressing concern here is that super NMOS draws power whenever Y is zero whenever Y is stable zero NMOS is on PMOS is also PMOS is on Y zero means one of the input is one one of the input values that NMOS is one so NMOS is conducting so now there is a direct path we will go back to the previous process so whenever Y whenever this node is zero that means this node has a path from ground this is the ground so this has a path from ground plus this is on so there is a path now we need to ground with resistance offered by this PMOS this PMOS there is some resistance of it and this NMOS there is some resistance of it but otherwise there is a path that exists compared to CMOS where there is almost no power connected almost no current and very small heat wave current whenever Y is either zero or either one but in this case it is not not so in this case it draws power whenever Y is zero this is static power P is equal to I need it and this now consider a bit chip or even a moderate size chip thousands of thousands and more this can be a really big problem that is why SUDO and MOS was one of these it might have been in use otherwise at a generous in this way SUDO and MOS is not used just because so the special case one special case can be we can use SUDO and MOS sparingly for wide nodes now what is special about nodes if you write down the proof table for nodes you would realize that let us say you have a three input node the three input node will give one only for one condition when all three inputs are zero otherwise it will be zero most of the time what it means is that the probability of a three input node going to zero is seven by eight which is very very high probability that means this the output is zero most of the time but now we want to turn so we want to turn off P MOS for node in use so the probability of y being zero in this case is very very high so y being zero is very very high and we exploit that probability and we connect an enable signal and P MOS and so this enable signal this P MOS would be disabled for majority of the time what this does is it gives us a node which is lower in area obviously we have an extra circuit for enable but that is very small design so we have a node which is less in area and probably faster than regular signal this is one special case where through to M MOS can be used but for our limitation of this course this is the preview of this course and when we use synthesis we will not encounter any suitable all circuits used in standard cell library all designs are C MOS or they have transmission but it is good to know that to reduce area or to reduce transfer sound or to make the circuit faster what else can be done so this is an example we have a second set of logic family it is very interesting concept it is just an extension of C MOS it does not result into a decreased transfer sound so the area in fact increases a bit but it is very very fast in some cases and in fact it is used in some special design now let us compare this three logic family the inverters are drawn here so one is static other is through to M MOS third is dynamic so the difference dynamic has over static is that through to M MOS it was P MOS which is always on dynamic there is a extra input this extra input is for let us call it top now dynamic so this P MOS will be on when clock is 0 we call this pre-charge mode this P MOS would be off when clock is 1 we call it evaluate mode now what happens during this mode now pre-charge as the name suggests pre-charge means pre-charging the node to some value so in this case we are talking about node 1 so what this clock input does is whenever it is 0 y is pre-charge to vdd so there is a path from vdd to y and y gets pre-charge so this time in diagram it tells us that y remains 1 whenever it is pre-charge mode whenever this clock goes to 1 the P MOS becomes off and now y is ready to take on whatever we do so whenever if a is 0 now this n MOS is off y is 1 because it was pre-charge already when a is 1 n MOS is off y is 0 because it connects to vdd now it connects to ground mode but correspondingly when you compare it to true to n MOS there is no path from vdd to y so in this case also just like c MOS only one thing is on at one time so during evaluate mode let us say if a was 1 y would go to 0 again at pre-charge y would go to 1 y is a dynamic it is dynamic because y holds the value let us say if a was a continues to be 0 n MOS would be off and y would be holding 1 even during evaluate mode it is not being charged it is being discharged so there is a dynamic charge there on y that is why it is called dynamic logic and plus we use a clocking signal to pre-charge and evaluate which is again a dynamic signal so you could say that the name comes from there now let us look at two interesting topics so one question comes that what is pull-down network what is in the earlier slide pull-down network is let us say a a is during the pre-charge itself a is 0 a is 1 that is n MOS is conducting so if n MOS is conducting then it is not a like it is not a good scenario because y is being driven by VDD and also by n MOS which is a problem we saw through n MOS so we do not want that so what we will do is which is again driven by clock so this clock so whenever during pre-charge mode this n MOS is this n MOS is off so it prevents by from getting it prevents via from getting the getting driven by VDD and ground at the same time so a typical dynamic logic would look like this so you have a put-in terminal logic would look like this you have put you have inputs going to a pull-down network f comprising fully of n MOS and you have a pre-charge transistor driven by clock and put-in we just remove the pull but you still need the pre-charge transistor now what happens to the logical effort so logical effort is a very good tool in comparing the capacitance so we again move that so so inverter 1 and 1 so a will always see an input value of 1 1C compare this with an inverter which a sees the value of 3 so g for this case for g for terminal logic becomes 1 by 3 again I will repeat a here sees the capacitance of 1C because of this n MOS because of this n MOS exceeds just 1C a corresponding unit C MOS inverter sees value of 3C 2C coming from the P MOS so g becomes g for terminal becomes 1 divided by 2 similarly P this Y sees 1C plus 1C which is 2C compare it with a unit inverter which has an output gap of 3C so P for terminal becomes 2 by 3 let us compare it go to the put it case again here a sees 2C Y sees 1 plus 2C divide by 3 in both the cases compare the unit inverter so we get a value of 2 by 3 and 2 by 3 again for NAND 2 we can do the same exercise Y sees 1C plus 2C 3C so P becomes 3 by 3 a sees 2 so G becomes 2 by 3 for put it case GD becomes AC screen so G becomes 3 by 3 Y sees 3 plus 1C so PD becomes 4 by 3 similarly you could do the same for NAND now we we can see that obviously the put it 1 adds 2 transistor extra to the C MOS the unput it 1 adds 1 transistor extra to dynamic dynamic logic we call them also terminal dynamic logic in fact adds transistor to C MOS so the area is more the area is more but on the other hand the loading on Y on A degree inputs the loading degree to Y because input is only connected to NM so P MOS so the capacitance is decreasing on inputs and correspondingly the circuit becomes faster so what did a dynamic logic do dynamic logic in fact use the similar concept as SUDO and MOS by realizing the logic function only by the pull down method it does not move the P MOS pull up method so in fact only I think that all the dynamic logic adds extra P MOS to the header in the 2P MOS on the put it 1 but it actually reduces from the circuit bit because the P MOS pull up to the network is not there so it takes SUDO and MOS and adds an implement over it it adds a plot just to prevent the current leakage the pull down method so now let's see so now there is one interesting concept called monotonicity in case of dynamic gates so dynamic gates require monotonically rising input during valuation whatever it means is that input should go from 0 to 0 that is no transition or 0 to 1 or it should remain as 1 it is not allowed for input and why is that now let's say so during a pre-charge mode why will always be 1 now let's say during evaluate mode A was 1 during the pre-charge mode and during evaluate mode A went to 0 now if A went to 0 then this is during evaluate mode the pre-charge one this is off and this is on this is on input and MOS so A goes to 0 why cannot go to 1 now why because during evaluate mode there is no path the path from VDD to Y does not exist this path does not exist so during evaluate there is no way Y can go to 1 you see the job of is on the on the T MOS which is given by a clock now if this T MOS is off which is the case during evaluate mode nothing else there is no nothing else more than that so Y will not become 1 and this is a problem this is an invalid condition for this again during Y will only become 1 during the pre-charge mode so output should have been but it does not rise during the evaluate mode now let us say the evaluate mode is longer and you expect the output to rise but it does not create the problem so that is why these gates are restricted but on the other hand a dynamic gate will produce a moment on it will be falling output during evaluation what does this mean this means so see the case when I connect one inverter so whenever A goes from 0 to 1 X goes from 1 to 0 or X going from 1 to 0 is not valid for the second for this dynamic logic so during pre-charge both X and Y are 1 A remains at 1 A remains at 1 so during evaluate mode X goes to 0 but now X going from 1 to 0 violates the input condition for the second inverter so Y will not rise and this is the problem so it is illegal for one dynamic gate to rise under dynamic gate what should we do now how do we construct circuits out of dynamic gate the answer lies in dominant dominant gate so what do we do in dominant is that we follow a dynamic stage with an inverting static gate so let us say this is a an experiment circuit this is a domino amp so this part here this part here is a dynamic NAND gate the NMOS network here is present in NAND gate and we add an inverter static inverter so this becomes NAND plus inverter becomes NAND and this the union of this dynamic NAND in a static inverter is called a domino amp the domino amp is simply a dynamic gate followed by a static 3 MOS input this solves the problem of monotonicity for us it produces monotonic output so for the case where the let us say W node was falling X now is rising W and it does not pose a problem for the next gate so for the next gate still you have X which is rising again Y falls and Z is fine since Y to Z is a static it does not have any restriction the logic works just fine so we could also draw a logic diagram here representing this gate so you have a dynamic NAND you have a dynamic NAND then a static inverter then again a dynamic NAND and again a static inverter so we convert this dynamic NAND to a domino amp this is a domino amp next input being the clock again this is domino amp now let us see what what domino optimization is so each domino Y Y is called a domino so each domino gate triggers the next one like a stream of domino that is what we call a domino logic so gates this evaluates sequentially what it means is that let us say you have N number of gates connected in fact let us go to the previous one you have a domino amp driving again domino amp all so the nodes X and Z and nodes W and Y will be pre charged at the same time because the same clock input goes to both of them so now for this logic there will be a pre charged cycle which will pre charge W and Y to and then there will be the evaluates cycle but evaluates cycle happens sequentially why because W will get the effect of A or B after some time Y will get the effect of X after some time so evaluates happen sequentially but pre charge happens entirely so evaluation obviously is more typical than pre charge so this is one example of a gate you have this is an example of a book list domino so this becomes S0 S0 and D0 S1 and D1 S0 and D2 and you have an inverting you have a static gate which converts to domino amp so high school static stages can perform logic what it means is that since evaluation is more critical than pre charge that means one logic level so logic level 1 is not critical it anyway gets to logic level 1 during pre charge but going to 0 is critical so the gates have to be skewed during one direction skewed gate means that it will be faster for one gate compared to the case the logic output going from 0 to 1 or 1 to 0 so skewed gate lets say will do a rise transition much faster than a low transition so this is what it says is there that high skewed static gate stages can perform logic during domino optimization now there is a very interesting concept called domino dual gate domino usually domino only performs non inverting function please remember domino is dynamic plus 1 inverter dynamic gate performs simply like few months performs non inverting function but we add an inverted way to make the domino output domino gate and domino only performs non inverting function so how do we now and or and not the three basic gates we need now we do not have an inverted way so what do we do we make something called a dual gate domino now dual gate domino the structure is like this so this yh is an input yi is sorry yh is output yi is invert of yh so yh and yi the outputs of dual gate domino are complementary to each other the inputs are also like that so 1 let us say s gets inputs regular inputs s bar gets complementary inputs so dom 2 and a domino what it does is that it takes 2 and complementary inputs and correspondingly gives 2 and complementary outputs so if we get and take i nothing but yh and yi so whenever they are 0 that means nodes where are 1 these nodes are 1 that means it is in pre-charge stage so whenever pre-charge happens whenever pre-charge happens these nodes the nodes will do these nodes gets get pre-charged and only in this case the outputs yi and yh are not complementary so they are both 0 otherwise during all these stages they are complementary and they will never become 1 and 1 both this is invalid they will never become 1 and 1 let us see an example of a dual gate domino so since they produce complementary outputs let us see an example of i and yh so the principle here is that you need let us say you have a 2 input gate so you need 2 regular inputs a and b a h and b h a h and b h you also need the inverted of this so you have a inverted and b inverted a i is nothing but complement of a h the function here the function represented by a h and b h will be complementary the function represented by a i and b h so on one side you make an AND connection other side you made a or connection now let us see one on the right hand side this is a h regular inputs i will call them simply a and b so a and b is inverted so this is a and so sorry this is NAND function a and b complement because it is an NMOS it is a and b complement goes to an inverter becomes a and b on the other hand side the pull down logic is a invert or b invert a invert or b invert a invert or b invert invert so a invert or b invert invert becomes a invert into yeah so it becomes so the pull down network on the left hand side is a invert plus b invert and complete invert of that so it becomes a and b using the model it goes to an inverter becomes a and b so becomes a NAND function so pull down networks are also conduction complement the inputs are also complement three to each other the outputs are also complemented obviously the area as this but you get two you get two outputs but the number of inputs are also you have to also consider the availability of the invertive input but then circuits are again designed for optimise realising the fact that you have two outputs available which are conduction complement and you correspondingly optimise the design in the circuit this is a very interesting circuit of drawer and xr now what you could do is you could first draw a circuit just like AND and NAND so AND a two input AND needs for one function it needs two transistors in the pull down network the other one also needs two so you would assume that for XOR now XOR is a very interesting again so you see that it shares transistor so a XOR is so you have a I will just call a H A A it is ANDed with B INvert AND plus plus A INvert ANDed with B complement of that since it is a pull down network we have to have complement of that this node here is the complement of whatever we saw B INvert plus A INvert complement of that it goes to inverter gives the draw function similarly the node here seems to be XOR function you could try drawing it on paper and see that how it transistors are shared by sharing I mean that there are connections from previous circuit there is no sharing of nodes between the left hand this part and this part there is no sharing of nodes it is just that the one on the right hand side represents and the one on the left hand side is NAND there is no sharing but in the case of XOR and XOR there is sharing in the sense that the node here the node here is shared to this circuit and the node here is shared to this circuit now one let us look at what are the limitations or the advantage we will look at both the sides for dynamic process now a dynamic node as I mentioned before a dynamic node floats high during evaluation rest of our inverter the input is 0 the output is 1 during evaluate phase but that output is a hanging one that means it is not driven by reading over time it will lose its value the transistors are leaking the off-current is not exactly 0 so during a long evaluate time let us say but do not stay that one it will start losing its it will start degrading from it it will leak over time this time was formally released again now nanoseconds it will go off in nanoseconds it will retain the value now we use a keeper but we need a weak weak PMOS so that it does not fight evaluation so now we know that we need a keeper only for the case where y is 1 so y means also in this case the node is x so whenever x is 1 we need to keep charging it so whenever x is 1 what does it mean so it is an evaluate phase so this is off I will cut this off this part is off x gets x the value on x being 1 tells us that it was 1 it was pre-charged and now this part is also off a 0 so now x is kind of a hanging one so we need to pre-charge x we need to keep feeding x to VDD and how do we do that if the inverter is already there we invert this and we give the output to a PMOS connected to VDD now x is 1 so now it keeps charging it in this case x is not floating and it keeps on charging to VDD for the complete evaluate phase so we are fine it will not leak so this is one problem we have to solve in governable or in binary states this problem is charging now let us look at this case this is a a dynamic NAND now in dynamic NAND the B is 0 1 input is 0 now A goes to 1 from 0 now A goes to 1 ideally the value on y should not change and NAND y here since B is 0 it is not connected to ground y was let us say already 1 it was pre-charge to 1 now the value on y should not change because B still is 0 but what happens this here conducts this and MOS here conducts and now let we could say that x and y are similar nodes so the capacitance of x will now affect the node y and the value on Vx Vx will be equal to Vy because this is conductive Vx is equal to Vy now will become Cy upon Cx plus Vy into Vd because there is some voltage drop the value on y is not in fact Vd this is lower than Vd how much lower depends on the capacitance Cx now this problem will not occur in 2 cases case 1 if we are able to make Cx 0 or case 2 when Cy is much much greater than Cy how do we do that to make Cx 0 what we do is we charge the node we also pre-charge node x in fact we typically need to pre-charge every such node if you have like a pre-down of it we have to pre-charge even that intermediate nodes all intermediate nodes have to be pre-charged to prevent this what pre-charging means pre-charging means actually making other thing I talked about was making Cy a bit but then Cy will be big only when the load is higher so big load capacitance Cy also help and again this is a disadvantage that a big load obviously will take lot of time to charge up or charge down but so we saw one problem of leakage we saw problem of leakage how to solve it we saw that we need to add a keeper so see now we are modifying a dynamic circuit to reduce the or to remove the incompetency compared to Cy we are actually adding logic so here we added a pmos again we added a pmos to pre-charging so the advantage the area advantage it has over a regular pmos it is kind of between the nodes even when you most specifically so when you consider small gates when you consider gates like 2 input man 2 input nodes majority of the gates are towards the input area advantage offered by dynamic logic or a dominant weighted pmos it might be even bigger than the corresponding static scheme other thing other problem is the third problem is the noise sensitivity the dynamic gates are very very sensitive to noise why because the input high value VIH is equal to B2M it means that any nmos here let us go back yeah let us go back to the inverter so see this dynamic inverter now let us say the input on A is 0 nmos is not conducting so VIH is funny but now let us say there is a bump on it there is a noise on it A was 0 and now there is a slight bump slight noise on it and A goes low again this is what we call noise that is unwanted value changes unwanted voltage there is changes on inputs it is called noise now what happens to nmos here let us say the phase is evaluated it is not a feedback it is an evaluate wave now this nmos starts conducting for this time for this amount of time whenever there is a noise on A and if only if the noise on A is such that the level exceeds the threshold voltage of nmos so this input here is more than VT of nmos now why we will start feeling the effect of this this does not happen in an inverter you see that in a started thing of inverter the noise margins are very very high in a circuit it does not happen there because you have both nmos and tmos now why starts why has the effect of A even when there is a noise of A on A which is as small as VT now let us let us sit in some value so VT 5 volts a VT let us say would be typically 0.7 volts so if the output is getting affected even when input is 10 percent even 10 percent of VT 10 to 15 percent of VT the null margin is very very low that is why we say that the dynamic gates have a low noise margin and this is one major disadvantage which prevents a more wide use of these so the very very sensitive noise again outputs because that outputs are floating in some cases let us say we do not have a feedback Vmos we do not have a keeper Vmos in that case output is floating and a floating output is more susceptible to noise a regular output driven by either VVV or ground is actually a very good very robust point it will not see much noise effect but a floating output any small noise can affect its value what are the noise sources noise sources are capacitive crosstalk this capacitive crosstalk is a very very important thing we will deal with we will talk about it a lot in unit 3 and 4 charge sharing capacitive crosstalk simply means that this gate will not be isolated there will be lot of gates there will be neighboring gates in the chip let us say we design a part with the dynamic logic each of those gate nodes and the wires will have some capacitance and those capacitance will affect the input and the output nodes of the dynamic gate and since the inputs and outputs are not very noise they do not have very good noise margin so they will be affected charge sharing we saw an example of charge sharing there will be a power supply noise the power supply is not always speak VVV there are some details there the noise coming from earlier stage and there are lot of noise sources so summary Domino logic is very very attractive for high speed circuit it is about 1 to 1.5 to 2X faster than static cleaner why is it faster only because inputs and inputs and outputs do not see the amount of capacitance as seen by the static cleaner we replace the pull-up network by a clocked CMOS but there are many challenges we saw monotonicity we saw leakage we saw charge sharing noise margin since we are talking about speed Domino logic is very very fast compared to static CMOS they are used in very high performance microprocessor and not for the complete microprocessor design they might be used for a part of the microprocessor which has to for example ALU now in automatic logic unit let us say the automatic part has adders has big adders and now those adders can use Domino logic and the performance of that adder actually determines the performance can determine the performance of a complete signal because big adders take lot of time so we could replace that in some some companies they might be doing, they might be replacing those adders design they might be converting from CMOS static CMOS dynamic logic I am not sure I personally have not seen any Domino logic design or dynamic gate design but I have heard it being used in some other so summarizing we saw two logic families SUDO and MOS and dynamic or Domino both strive to achieve higher performance by by getting rid of the performance since SUDO network for CMOS is the major source of input and output for CMOS SUDO and MOS suffers from a power issues and therefore it is not in use anymore it suffers because at one time whenever the node output mode is zero both CMOS and MOS are conducting and there is a big leakage current Domino logic or dynamic gate strive to solve this problem by having a problem but the problem they have is of monotonicity, leakage, charge sharing and all so again I would like to stress that we spend from the static CMOS so so when we go on we will see the algorithm and all those circuits, all those standard design are using static CMOS so we will not see any Domino, any dynamic gate any SUDO and MOS this is more to stress the point that different logic families do exist they are used for very special speed of paramount important and to appreciate the robustness of static CMOS it might be slow it might be region area but it is very very robust and that is the major that is the and one more thing that we call in Domino we have the clock input so again routing clock to thousands of parameters having extra input like clock it goes everything is not easy the routing resources would be huge and so the area transfer sounds will not be meeting but the higher area so it is not an advantage having an extra input as well the static CMOS is very robust it needs it does not need a clock except for sequential elements the noise values are very very high and it is reasonable that is why it is more popular