 Hello and welcome to this presentation of the STM32 tamper and backup registers. It covers the main features of this peripheral, which is used to provide security against tamper events. In the STM32G0, two separate units are present, tamper detection peripheral and real-time clock, called TAMP and RTC. Backup registers are contained in the TAMP block. In the STM32F0, a unique block is in charge of both tamper and RTC units. The TAMP peripheral features 532-bit backup registers used to preserve data when the main supply is off. These backup registers can be used to store secure data as they are erased when a tamper event is detected on the tamper pins or on some internal events. The tamper detection is functional in low-power modes when the VBAT domain is supplied by a backup battery. The anti-tamper circuitry includes ultra-low-power digital filtering, avoiding false tamper detections. The key features of the TAMP are 20 bytes of backup registers split into 5 32-bit backup registers. These registers are preserved in all low-power modes and in VBAT mode and are erased when a tamper detection event occurs on any one of the two tamper pins or the four internal tamper events. Regarding external tamper events, software can select whether backup registers are erased when the tamper event is detected. The two tamper pins are available in VBAT mode. The external tamper events can be detected on a programmable edge or on level with a configurable filter and using an internal pull-up in ultra-low-power mode. A timestamp function is used to save calendar contents in timestamp registers depending on any tamper event. Here's the Tamplock diagram. The TAMP has two clock sources. The TAMP clock named RTC clock is only used for the tamper detection in level detection mode with filtering and the APB clock is used for TAMP and backup registers read and write accesses. Tamper edge detection or internal tamper detection do not need any clock. The TAMP clock can use either the high-speed external oscillator divided by 32 called HSE. The low-speed external oscillator called LSE or the low-speed internal oscillator called LSI. Only LSE or LSI are functional in stop and standby modes. Only LSE is functional in shutdown and VBAT modes. Several internal features can generate a tamper event, LSE monitoring, HSE monitoring, RTC calendar overflow, and ST manufacturer readout. By default, all tamper detection events will erase the backup registers. The TAMP embeds ultra-low-power tamper detection circuitry. The purpose is to detect physical tampering in a secure application and to automatically erase sensitive data in case of intrusion. Two tamper pins and events are supported and are functional in all low-power modes and in VBAT mode. Detection can be edge or level triggered and the active edge or level is configurable for each event. A pre-charged time is determined by the TAMP preach bits in order to support large capacitances on the TAMP IN X inputs. A tamper event can generate a timestamp event which can be used to record the date of the intrusion attempt. The capacitor shown in the figure perform filtering. If no external capacitors are explicitly connected to a tamper input, they provide a model of the trace capacity. Note that an external pull-up is required in edge detection mode. In level detection mode, the internal pull-up is used as explained in the next slides. The tamper detection circuit includes an ultra-low-power digital filter. The internal IO pull-up can be used to detect the anti-tamper switch state. The IO pull-up is applied only during the pre-charging pulse in order to avoid any consumption if the tamper pin is at a low level. The pre-charging pulse duration is configurable to support different capacitance values and can be 1, 2, 4, or 8-tamp clock cycles. The pin level is stamped at the end of the pre-charging pulse. A filter can be applied to the tamper pins. It consists of detecting a given number of consecutive identical events before issuing an interrupt to wake up the device. This number is configurable and can be 1, 2, 4, or 8 events at a programmable sampling rate from 1 to 128 Hz. This figure illustrates tamper detection using the internal pull-up. The internal pull-up can be applied for 1, 2, 4, or 8 cycles. If the switch is opened, the level is pulled up by the resistor. If the switch is closed, the level remains low. The input voltage is sampled at the end of the pre-charge pulse. The tamper detection circuitry can also be used to generate interrupts or trigger events. Each tamper interrupt can be individually enabled or disabled. Each external tamper event can be individually configured to erase the backup registers or not. Each external tamper event can be individually configured to generate a hardware trigger to low power timers. This takes advantage of the digital filtering present on these IOs for interrupt or trigger generation. All interrupts can wake the processor up from all low power modes. The detection on all tamper pins and internal tamper sources can generate an interrupt. Any tamper detection circuit can be enabled or disabled by programming the TAMP CR1 register. If it is enabled and a tamper event is detected, the corresponding flag is set in the TAMP SR register. The TAMP IER register masks or enables the tamper event interrupt. The interrupt service routine can easily determine which tamper event has occurred by reading the TAMP MISR register which contains flags identifying the source of the tamper event interrupt. The nested vectored interrupt controller, NVIC, has a unique input related to RTC and TAMP modules. The output of the OR gate combining all tamper interrupt requests is also connected to the extended interrupt controller or EXTI as a direct line type which is required to generate a CPU event wake up signal or request a system and core wake up. The TAMP peripheral is active in all low power modes and the TAMP interrupts cause the device to exit the low power mode. In stop 0, stop 1 and standby modes, only the LSE or LSI clocks can be used to clock the TAMP. Only the LSE is functional in shutdown mode. This is a list of peripherals related to the real-time clock. Please refer to these peripheral trainings for more information if needed. Real-time clock, reset and clock control, power control, extended interrupt controller, nested vectored interrupt controller.