 Hello, and welcome to this presentation of the STM32L5 Digital to Analog Converter. This block is used to convert digital signals to analog voltages, which can interface with the external world and also with on-chip peripherals such as comparators and the operational amplifiers. The STM32L5 Digital to Analog Converters converts 8 or 12-bit digital data to an analog voltage. DAC module has two converters that can work synchronously or asynchronously. A low-power sample and hold mode is also integrated. The DAC can interface with external potentiometers or bias circuitry. It can also create voice and arbitrary signals. The Digital to Analog Converter inside STM32L5 microcontrollers offers simple digital to analog conversions in an 8 or 12-bit mode. The DAC outputs can have a low impedance buffer to drive external loads. Its sample and hold mode can reduce the power consumption significantly. The two converters within the same DAC can be synchronized with each other. The input data can be transferred by DMA, which offloads the CPU. It also integrates small logic to generate noise and triangle waveforms. The DAC output data is updated by a complex triggering system based on software requests, timers, and EXTI. Vref Plus is used as a positive voltage reference. An input reference pin, Vref Plus, shared with others analog peripherals is available for better resolution. An internal reference voltage buffer can generate the reference voltage on the same pad. Output buffer's voltage offset is calibrated. This calibration is performed at the factory, loaded after reset. The user calibration can be done when the operating conditions differ from nominal factory calibration conditions, and in particular when VDD or VDDA voltage, temperature, or Vref Plus values change and can be done at any point during application by software. Here you see the simplified block diagram of the Digital to Analog converter. This DAC block is supplied by VDDA and uses Vref Plus as a voltage reference. The Digital to Analog converter is an APB slave that supports DMA requests to fill the data hold register. Either of the DAC OutX signals can be disconnected from the corresponding output pin which can be used as an ordinary GPIO. DAC OutX signals can use an internal pin to connect to on-chip peripherals such as comparators and op-amps. DAC Output channels are buffered or non-buffered. Sample and hold block use LSI or low-speed internal oscillator clock source and are operational in stop mode for static conversions. The content of the data hold registers is transferred to the corresponding data output register when a trigger condition is detected. This includes software triggers. Then the content of the data output register is transferred to the converter. The output buffer has mechanism to calibrate the voltage offset. The STM32L5 implements one DAC unit. DAC1 supports two channels. DAC1 can output to GPIOs and it can be connected to comp and op-amp units. The utilization of output buffers is optional for DAC1. DAC1 maximum speed is one mega-sample per second. The DAC OutX can use an internal pin connection to on-chip peripherals such as comparator and operational amplifier. The DAC OutX GPIO can be used for another purpose. Connecting the internal DAC output to a comp INM input defines the reference voltage of the comparator. Connecting the internal DAC output to an op-amp VINP input can be used to bias the op-amp DC point or amplify the analog voltage. The DAC can support different input formats. In 8-bit mode, it is a right aligned 8-bit data format. It also accepts the unsigned and signed data format. In dual-channel mode, it is an 8-bit plus 8-bit data format in order to provide input for two DACs. In 12-bits plus 12-bits, either a right or left aligned mode can be used for input data. Data held in these registers are transferred to the related converters either synchronously, for instance for stereo audio or asynchronously. This means that the two channels can operate independently. DAC output conversion is started by writing to the data hold register using software. Ten different timer outputs and an external I.O. or software can trigger a DAC conversion. When a software trigger is used, the content of the data hold register is transferred to the corresponding data output register after one APB clock cycle. When a trigger occurs in trigger mode, the content of the data hold register is transferred to the corresponding data output register after three or eight APB clock cycles, depending on the APB clock frequency. The sample and hold feature maintains the DAC output voltage while not actively driving continuously. It relies on an internal or external capacitor that will hold the voltage level at the end of the sample period. Then the DAC output can be set in high impedance. Of course, the capacitor will discharge over time. That is why a refresh period has been defined. Upon expiration of the refresh period, the DAC output will be actively driven again to recharge the capacitor. The digital to analog converter can work intermittently, charge the external or internal capacitor and be powered down while the output voltage is kept on the hold capacitor. After the refresh period, the DAC is powered back on again and recharges the hold capacitor. When the DAC is configured in sample and hold mode, it is able to generate its converted output voltage and active circuitry can be turned off. In this mode, the DAC core and all corresponding logic and registers are driven by the LSI clock or LSICK in addition to the DAC-PCLK clock, allowing the usage of the DAC channels in deep low power modes, such as stop mode. The logic in charge of scheduling refreshes only requires the LSI clock. In doing so, the DAC is only active during very low duty cycles, sample and refresh, resulting in very low power consumption. The duty cycle program is very flexible and autonomous. The capacitor can be external or internal. When it is external, the buffer can be used and the DAC's output can also be routed to internal components, such as embedded comparators. When it is internal, an embedded capacitor is used and the DAC's output is routed only to internal components. The charging time depends on the capacitor value. The timings for the three phases above are in units of LSICK clock cycles. The DAC digital interface integrates two special signal generators. The linear feedback shift register can create the noise signal for the DAC input. Each trigger updates the DAC output data by an LFSR block. The up-down counter with a programmable count value can create triangle wave data which can update the DAC output data. The data can also be updated by a trigger signal. The DAC can also create DMA requests from the trigger signal. Once a trigger is detected, the data hold register value is then transferred to the data output register. Then the DMA request is generated to obtain the new data for the data hold register. As the update of the output data register is initiated directly by the trigger signal, the DAC output signal will not have jitter, so that it can create a stable sampling time signal output, making it easy to filter out the sampling frequency. To transfer data from memory, a DMA request can be generated. The DAC DMA request is not queued so that if a second external trigger arrives before the acknowledgement of the first external trigger is received, first request, then no new request is issued and an underrun flag is set that causes a maskable interrupt request. The digital to analog converter is active in the following low power modes, run and sleep. In stop 0 and stop 1 modes, it remains active when sample and hold mode is selected. In standby and shutdown modes, the DAC is powered down and it must be re-initialized afterwards. The following table shows some performance parameters for the digital to analog converter. The DAC can work between 1.8 and 3.6 volts. When DAC output buffer is on or DAC outpin is connected, the minimum VDDA voltage value is 1.8 volts. 10-bit monotonicity is guaranteed. When operating at 1 mega sample per second, power consumption is 185 microamps when the buffer is enabled and 155 microamps when the buffer is disabled. By using sample and hold mode, the current consumption can be drastically reduced. Depending on the condition and the hold capacitor characteristics, less than 1 microamp current consumption is possible for this mode. The DAC buffered output has a settling time of 1.6 microseconds with 50 picofarad load. The DAC can handle a sampling rate of 1 mega sample per second. This is a list of peripherals related to the DAC. Please refer to these peripheral trainings for more information if needed. Application notes dedicated to DAC topics are also available.