 Hello and welcome to this presentation of the STM32-C0 Reset and Clock Controller. The STM32-C0 Reset and Clock Controller manages system and peripheral clocks. STM32-C0 devices embed two internal oscillators and two oscillators from an external crystal or resonator. Note that no PLL is present in the STM32-C0. Many peripherals have their own clock independent of the system clock. The RCC also manages the various resets present in the device. The STM32-C0 RCC provides high flexibility in the choice of clock sources which allows the system designer to meet both power consumption and accuracy requirements. The numerous independent peripheral clocks allow a designer to adjust the system power consumption without impacting the communication board rates and also keep some peripherals active in low power modes. Finally, the RCC provides safe and flexible reset management. Safe and flexible reset management without any need for external components reduces application costs. The RCC manages three types of resets. The system reset, the power reset and the backup domain reset. The peripherals have individual reset control bits. The first type of reset is the system reset which resets all the registers except reset flags present in the RCC control and stages registered too. It doesn't reset the RTC domain either. The system reset sources are the external reset generated by low level on the NRST pin, a window watchdog event, an independent watchdog event, a software reset request, a low power mode security reset which is generated when stop, standby or shutdown mode is entered but is prohibited by the option byte configuration, an option byte loader reset and a brownout or power on reset. The reset source flag can be found in the RCC control and status register. Two fields in the option bytes are used to configure the NRST pin. NRST mode selects the operation mode of the NRST pin, input output reset, input only reset or GPIO. IRHEN stands for internal reset holder enable. When this mode is enabled, the NRST pin is driven low until its voltage level goes under the voltage input low threshold. Upon power reset or wake up from shutdown mode, the NRST pin is configured as reset input output and driven low by the system until it's reconfigured to the expected mode when the option bytes are loaded. Here's the simplified block diagram of the system reset. All internal reset sources provide a reset signal on the NRST pin which can be used to reset other components of the application board. In addition, no external reset circuitry is needed due to the internal glitch filter and the safe power monitoring feature which guarantees the reset of the application when VDD is below the selected threshold. The internal pull-up on the NRST pin, which maintains a high level when no reset signal drives it low, is deactivated when an internal reset is driven in order to reduce power consumption under reset. Additionally, except the debug pins and some test pins, all IO pins are placed in analog mode during and after reset to eliminate power consumption through the Schmidt trigger when the IOs are floating under reset and before software initialization. The purpose of the reset holder is to maintain NRST driven low until the voltage level of this signal goes below VIL. This is useful when the NRST line has an important capacitive load. The second type of reset is the power reset. The brownout reset or bore resets all registers in V-core power domain. When exiting standby mode, all registers powered by the regulator are reset. When exiting shutdown mode, a brownout reset is generated. The third type of reset is the RTC domain reset which affects the LEC oscillator, the RTC and the RCC control and status register 1. Note that backup registers are outside the V-core domain. The RCC offers a large choice of clock sources which can be selected depending on low power, accuracy and performance requirements. STM32C0 devices embed 2 internal clock sources, a high speed internal 48 MHz RC oscillator or HSI48 and a low speed internal 32 kHz RC oscillator or LSI. STM32C0 devices embed 2 oscillators for use with an external crystal or resonator. A high speed external 4 to 48 MHz oscillator or HSE clock security system and a low speed external 32.768 kHz oscillator or LSE also with a clock security system. The I2SCK in-pin is one of the possible clock sources of the I2S1 peripheral. STM32C0 devices doesn't embed PLL but the HSI48 provides the max frequency of the device which can be then reduced by clock dividers. The system clock can be derived from the high speed internal 48 MHz RC oscillator or HSI48 or the high speed external 4 to 48 MHz oscillator or HAC. The AHB clock, called HCLK, is derived by dividing the system clock by a programmable pre-scaler. The APB clock, called PCLK, is generated by dividing the AHB clock by programmable pre-scalers. The RTC clock is generated by the low speed external 32.768 kHz oscillator or LSE, the low speed internal 38 kHz RC oscillator or LSI or the HAC divided by 32. The LSE can remain enabled in all low power modes except shutdown. The LSI can remain enabled in all modes except shutdown and standby. Each oscillator can be switched on or off independently when it's not used to optimize power consumption. The high speed internal oscillator is a 48 MHz RC oscillator which provides 1% accuracy and fast wake up times. The HSI48 is trimmed during production tests and can be user trimmed. The HSI48 can be selected as clock at wake up from stop mode and as the backup clock if an HAC failure is detected by the clock security system. The HSI48 can be automatically awakened up when exiting stop mode in order to make it available for peripherals when it's not used as the system clock. The USART1, USART2 and I2C1 peripherals can enable the HSI48 oscillator even when the MCU is in stop mode if HSI48 is selected as clock source for one of those peripherals. This table provides the characteristics of the HSI48 clock. The HSI48 accuracy can be improved by implementing a trimming procedure based on Tim14, Tim16 and Tim17 channel 1 input capture. A clock reference such as HAC divided by 32 or LAC is used for a higher accuracy capture of the current value of the counter clocked by HSI48. The HSI clock has a typical 1.4 microsecond start up time while the HAC clock has a typical 2 ms start up time. The high speed external oscillator provides a safe crystal system clock. The HAC supports a 4-48 MHz external crystal or ceramic resonator and also an external source in bypass mode. A clock security system allows an automatic detection of HAC failure. In this case a non-maskable interrupt is generated and a break input can be sent to timers in order to put critical applications such as a motor control in a safe state. When an HAC failure is detected the system clock is automatically switched to an internal oscillator, the HSI48, so the application software doesn't stop in case of crystal failure. In external source mode also called HAC bypass mode an external clock source must be provided. It can have a frequency of up to 48 MHz. The external clock signal, square, sinus or triangle must drive the OSC in PIN. The OSC out PIN can be used as GPIO or it can be configured as an OSCEN alternate function to provide a signal enabling the stop of the external clock synthesizer when the device enters low power modes. STM32 C0 devices embed an ultra low power 32 kHz RC oscillator which is available in all modes except shutdown. The LSI can be used to clock the RTC and the independent watchdog. The accuracy of the LSI is plus or minus 1.5% over temperature and plus 0.1 minus 0.2% over voltage. The LSI consumption is typically 110 nm. If the independent watchdog or IWDG is started by either hardware option or software access the LSI oscillator is forced on and cannot be disabled. The 32.768 kHz low speed external oscillator can be used with external crystal or resonator or with an external clock source in bypass mode. In bypass mode an external clock source must be provided. It can have a frequency of up to 1 MHz. The oscillator driving strength is programmable. It can be changed at runtime using the LSI DRV bit in the RCC control and status register 1 or RCC CSR1 to obtain the best compromise between robustness and short startup time on one side and low power consumption on the other side. A clock security system monitors for failure of the LSI oscillator. In case of failure the application can switch the RTC clock to the LSI and an NMI is automatically generated. The CSS is functional in all modes except shutdown. It's also functional under reset. The LSI can be used as the source clock of CIS CLK. SDM32C0 introduces oscillator pins sharing between high speed and low speed oscillators. This remapping option offers high level of flexibility especially useful on low pin count devices. Thus PC14 OSC-X in and PC15 OSC-X out are shared by both LSI and HAC and the two clock sources cannot be used simultaneously. The system clock is selected among the LSI, LSI, HSI48 and HAC clock sources. The maximum system clock frequency is 48 MHz. The APB bus frequencies are up to 48 MHz. Upon system reset the HSI CIS CLK derived from HSI48 oscillator is selected as system clock. When a clock source is used as a system clock it's not possible to stop it. The various clocks can be output on IO pads. The MCO and MCO2 pins output independently of each other the clock selected from LSI, LSI, CIS CLK, HSI48 and HAC. The multiplexes for MCO and MCO2 respectively are further divided by a programmable ratio. The LSI pin allows outputting of low speed clocks, LSI or LSI. The low speed clock output is available in stop mode. The dynamic power consumption can be optimized by using peripheral clock gating. Each peripheral clock can be gated on or off in run and low power run modes. By default the peripheral's clock is disabled except the flash memory clock which is enabled by default. When a peripheral's clock is disabled the peripheral's registers cannot be read or written. Other registers allow for configuring the peripheral's clock during the stop and sleep modes. This also affects stop mode for peripherals with an independent clock active in stop mode. These control bits have no effect if the corresponding peripheral clock enable is cleared. By default no active peripheral clock is gated in stop, sleep and low power sleep modes. When a peripheral isn't needed its clock enable bit should be cleared to reduce the power consumption. This slide lists the RCC interrupts. The LSE and HAC clock security systems and all oscillator ready signals can generate an interrupt. Note that the flag indicating an automatic clock switch in case of external LSE or HAC loss has to be cleared in the NMI interrupt service routine. The RCC unit implemented in the STM32C0 is like STM32G0 and offers new features in comparison to STM32F0 microcontrollers. The NRST pin has three possible usages. Reset input used by an external logic to signal reset condition to the STM32C0. Reset input and output or the legacy mode any valid reset signal on the pin is propagated to device internal logic and all internal reset sources are externally driven through a pulse generated to this pin. GPIO in this mode the pin can be used as standard GPIO. Reset is only possible from the device's internal reset sources. The reset holder option can be used if enabled in the option bytes to ensure that the pin is pulled low until its voltage meets the VIL threshold. No PLL is embedded for cost purposes. The HAC48 oscillator allows the system to run at maximum speed of 48 MHz. The clock security system or CSS also monitors the LSE and detects failures. If the low speed external 32.768 kHz oscillator or LSE is used as system clock and a failure of LSE clock is detected the system clock switches automatically to the low speed internal 32 kHz RC oscillator or LSI. Regarding the STM32C0 the timer clock TIMPCLK runs at PCLK frequency if the APB prescaler division factor is set to 1 or twice the PCLK frequency otherwise. So the max frequency of timers is CCLK frequency. In addition to this training you may find the power control and interrupt controller trainings useful. For more details please refer to application note AN2867 an oscillator design guide for STM8S, STM8A and STM32 microcontrollers. Thank you for attending this presentation.