 So, welcome back, we are discussing finite state machine plus data path controller plus data path and we were discussing a particular example of greatest common divisor computation iterative computation and we had discussed the data outline the data path it is corresponding very long description and the controller for that which turned out to be a single which to begin with we designed a purely combinational controller. We found a bit of deficiency in that in the sense that the start signal was having too much priority as long as a start signal was high the system was not at all proceeding to the computations. So, then we outlined if once we if you change the protocol so that we can respond to the start signal as soon as possible then we will have to we will need extra states and the controller will be a more genuine multi state finite state machine instead of a purely combinational controller. So, let us quickly review that and discuss it further. So, the data path for GCD just to consolidate the picture in your mind will repeat quickly draw it bit more neatly this is the X resistor which is driven by output of a multiplexer and at this multiplexer is controlled by an output of a controller with the signal load X in and when this load X in is asserted the input from the external services X in is loaded into the resistor X. This is the clocked resistor otherwise if load X in is 0 then the input to X is going to be loaded with something that would depend on whether swap is asserted or not. If swap is asserted X is to be loaded with Y is swap is de asserted X is to be loaded with something called X minus Y which is the result of arithmetic logic unit which subtracts Y from X. This is the same Y which is going over here coming from somewhere else this is X which is coming from over here that is a picture for how X gets loaded either from X in when load X in is high or if when load X in is not high it will be loaded from either Y or the result of this ALU X minus Y depending on whether we swap or not. So, correspondingly this is Y, Y is a multiplexer here and again that multiplexer is similarly similar to that for X is going to be controlled by a control input in output from the controller which is input to the data path say load Y in and when that load Y in is asserted Y in which is the input ready at the port of this GCD module is going to be loaded into this clocked resistor otherwise like in this case Y is going to be loaded either with depending on swap either with X or with Y. We also require a comparator and a zero checker right other than this. A comparator will need to compare X and Y tell us with indicate to us through this signal whether X is less than Y and a zero checker is going to look at Y whether Y is zero or not and tell us whether Y is equal to zero or not. This Y is coming from over here I guess this is slightly neater diagram for the data path we have shown all the data path components that we require. So, now we had started working I mean on the protocol like where the start signal is quickly responded to and that required a use of a state called state idle in which the system is kind of waiting for the start signal to be asserted and when start is not asserted stay in this state. Once the start signal is asserted then the system in the next clock cycle would move to a state s t loop but before it by the end of the current cycle before it moves to the state load X in load Y in would have been asserted by the controller. So, as to ensure that at the end of this particular clock cycle while moving from state idle to state loop X in and Y in would be loaded into X and Y. So, at the beginning of the clock cycle when the system has moved to state loop X and Y have been loaded with input values. So, now we are ready to compute then we will check. So, this is where this system will reside for a few more clock cycles as long as we have interesting X and Y inputs. In the beginning of every clock cycle this will check whether Y is equal to 0 or not either Y is 0 or Y is not 0. So, if Y is 0 then we know that computation is over the controller asserts the ready signal which is the output of that controller and goes back to the idle state. So, that it is ready for like in taking in the next input X in and Y in to X. If Y is not equal to 0 then we are still have some work to do and that would exactly what to do will depend on whether X is less than Y or whether X is not less than Y. In this case swap signal will be asserted and in next clock cycle we again go to this same state where we will behave the actions of this data path would be again dependent on X Y equal to 0 or X less than Y and so on. So, we will go back in this state we still have some more computation to do. If X is not less than Y then we do not swap and in the next clock cycle we go back to this state. So, this is the state diagram that we have arrived at. To make this unambiguous or like to connect this up correlate this with verilog to understand the verilog's semantics and synthesis process it would be instructive to write the verilog code for this controller. Note that data path has not changed. So, just the controller changing and with the help of that changing the controller we are being able to implement a different protocol of the way we respond to start signal and so on. So, the verilog for generation of this I mean like the state machine. So, first let me describe the state transition logic. State transition is taking place at the triggering edges of the clock that is say positive edge of the clock. So, it is typically is going to be described using a case statement depending on what the current state is we have different cases. The current state is state idle then we stay in the same state as long as start is 0, but if start becomes 1 start is asserted then in the next clock cycle we will be ready to move to state loop. Else we stay this is not required else we stay back in the same state idle that is how we respond while we are in the state idle. So, the transition in the next clock cycle we will move to state loop if start has been found to be asserted like in a stable at the end of this clock cycle and otherwise we stay back in this loop. So, this is corresponding to this particular picture. If start is asserted we are going to move to state loop if start is not asserted we are going to stay back in this state. Now, the logic if the system is in state loop the state transition logic not the logic for generation of the control signal that we will describe in a separate always block. So, here it would depend on whether first will the system will look at the status signal y equal to 0 which is coming from the data path this controller system will look at y equal to 0. If y is equal to 0 then we know that next state we are going to move to is idle state. So, waiting for next triggering next trigger for the system to start else the computation would depend on whether x is less than y or x is not less than y, but the next state is going to be the same. You notice that although in this diagram we have you know if y is not equal to 0 we have this for two further situations with x less than y or x not less than y, but that is for the output control signals control signals which are being generated by this controller, but the next state is going to be independent of whether this or this next state is going to be s t loop. So, as far as next state logic is concerned state transition logic is concerned this is sufficient to say this. In fact, this is also redundant because this is the wedlock semantics will tell us tell the synthesizer that the system the next in the next clock cycle we are staying back in this state. So, this would have been similar to this this else block is also redundant, but just for clarity we are I am putting it here. What else these are the only two states right we have completely captured how the transitions take place, but for completing the case statement we have to have some default and in which we really do not care, but just to be on the safer side we say that if some funny situation is there and anticipated like you know unclear values on the states signal then we move to state idle. So, this this wedlock code fragment captures the state transition logic. Now the logic for generating the control signal is also typically described using always block ok. So, this is the output logic output of. So, the outputs of FSM the control signals to the data path and also a signal ready which is output of this GCD subsystem ok. So, this is combinational logic. So, this will is going to depend purely on what the current state is and within that depending on current state you also look at the current input values to the controller which will be the signals x less than y or signal y equal to 0 and so on ok. So, we have to specify what will be the control signals the control signals are load x in I like in the case for seeing this purely combinational controller which we seen in the last class I use the default values I said a default load x in to 0 load y in to 0 swap to 0 ready towards to 0 and here I am only going to show the non default values. So, if in the state idle then only when start signal is asserted we will be doing something to this like the load x in and load y in signals will be asserted load x in will be 1 load y in will be 1 and we would have moved to that state loop as described in the other always block which is the state transitional description. So, nothing else as far as the output signals are concerned in state idle state loop let us look at the diagram for state loop in state loop the output signals will depend on whether y is equal to 0 then the ready signal will be asserted and if y is not equal to 0 it would depend on whether x is less than y or x is not less than y. So, if y equal to 0 then ready is 1 else if x less than y then swap is 1 else swap is at the default value 0 sorry the default is also required, but default whatever so I do not care really n case. So, I could just have an empty statement here let the default values remain as it is. So, using the blocking assignments and using specifying the defaults early enough and specifying non default values in this block of code I have completely described purely combinational logic for generation of output and this logic depends on the current state as well as the current inputs to the controller which are start y equal to 0 x less than y all the signals are playing a part in deciding the values output values of this controller which are some of them are input to the data path some of them are output to the external world. So, having seen the GCD example quite like you know and variation of that to illustrate the like need for typical need for a multi state finite state machine rather than purely combinational controller I will just for a change will move to a different example of again of FSM plus data path and it is a very simple example where the concept of multiple state will again be evident, but in a different context with a different requirement. So, this is the example of simple binary multiplication where let us ignore this let us assume that the binary numbers are positive non negative or positive numbers and we are going to multiply them using very simple the school grade multiplication system adopted for binary numbers. So, let us say the numbers are this is number 13 in binary this is number 5 the result should be 65 let us say the way this computation is done is as follows the shift the so called shift add approach shift and add algorithm which is very easy to hard wire and that is what we are going to see it as a FSM plus data path is as follows. So, we are going to maintain an accumulator where the multiplication will accumulate that accumulator will be initialized to it will be sufficiently big accumulator capable of storing the product this is x and this is y input x and y have been stored in to registers x and x in and y in have been assumed to be stored in registers x and y at the start of this computation of course, some of this register especially accumulator is going to be changing x will not be changing x is going to be repeatedly added y will be changing because we are going to look at the bits of y 1 by 1. So, assume that y is going to be put in some kind of shift register so that which will be shifting left 1 bit at per cycle at a time. So, the algorithm is as follows it looks at this particular MSB of y this is the let us say let me call this this is MSB of y it happens to be 0 because of that what we are going to do is simply shift since MSB y is 0 just shift. So, what have shift accumulator? So, the accumulator is going to be again shift and load accumulator we also for the next clock cycle we will we will also pop out this particular MSB of y. So, we will say shift y register to left. So, this is these are the actions we will be taking in this clock cycle. So, at the end of the clock cycle y would have been because of this control signal y register would have been shifted left. So, this MSB would have been popped out new MSB most MSB stands for most significant bit we will be looking at this particular bit in the next clock cycle. Accumulator would be loaded with the shifted version of the current accumulator just shift and load accumulator. So, here there is no difference it is going to be 0s all 0s x is going to be as it is in the next clock cycle because of the shift y left we are going to see 1 0 1 and 0. So, note that the 0 is the 0 was this particular 0 trailing 0 is not part of the original input and we are going to keep track of this with the help of a counter. So, I am not missed it out here, but assume that there is a counter which is keeping track of how many iterations we are progressing we are progressed in the next clock cycle when in the in the beginning of the clock cycle we have this situation y shifted accumulator has been loaded with the shifted version of that, but now we have interesting situation the MSB MSB is 1 since MSB of y is 1 is 1 we say shift and add load accumulator with the result of the adder and also pop out y by shifting that register to left. So, now what we get is to the accumulator we like you know accumulator is loaded again with the shifted version plus shift plus add. So, that is 0s plus 1 1 0 1. So, this is going to be the new accumulator x is going to be as it is and in the next clock in the beginning of the next clock cycle we will have this MSB will be 0 again MSB of y will be 0. So, now since MSB is this therefore, accumulator is going to be just loaded with a shifted version of it no addition will take place we will also be shifting y to left and let me also space something that missed out earlier will also be decrementing counter the counter which is going to keep track of how many iterations we have progress. So, in the earlier steps also I should specify that decrement count decrement count. So, all this kind of actions are being signals are being generated appropriate additions are being done some appropriate times shifting is being done loading accumulator is being done. So, because of this what we are going to get in the accumulator is shifted version of 1 1 0 1 what is remain x is not changing at all, but y is going to be now shifted further and for the last iteration we see that particular the last bit of y as the MSB now remember the y was 0 1 0 1. So, this is when the last iteration now because MSB is high MSB is of y is 1. So, therefore, accumulator is going to be loaded with the shifted version plus x and then at the same time we will instruct the shift register for y to shift to left and to instruct the counter to decrement. Now, what is the result that is going to be at the end of the clock cycle in the accumulator is going to be this shifted by 1 1 bit plus this particular number 1 1 0 1. So, let us calculate that. So, 1 1 0 1 0 0 and this for the 2 0 this is the 8 bit accumulator and 1 1 0 1. So, we get 1 0 0 0 0 0 1 0. So, what we end up here is 0 1 0 0 why would be now all 0s note that counter would have decremented to 0. Now, we know that we have done 4 iterations which are the 4 iterations iteration number 1 iteration number 2 3 and 4 at the end of this 4 iterations we should have we expect to have the result in accumulator about this result is 64 plus 1 this is 65 in decimal. So, it is exactly what we expected it to be 13 multiplied by 5 65 because this is 13 and y was 0 1 0 1 that is 5. So, we have this correct description of the simulation of this particular shifted add based algorithm. So, it is data path is going to be quite simple. So, it is quite instructive to look at this as an other example another example of F s simple as data path. So, what is the data path? So, what do you expect? We definitely require an adder we require a shift register for what? Shift register for y we require a multiplexer I mean most likely in most cases we require there is a role for multiplexers there is a role for ALU. We will see exactly we require a counter for keeping track of the count for updating the count what else to be require in this algorithm? A register several registers one shift register for y and registers for appropriately big register for accumulator and for x. x is in fact constant. So, we might be able to optimize it a little bit. So, let us start like you know placing this components and wiring them up. So, here is a big accumulator this is a clocked register I call it this accumulator. This accumulator is going to be taking at times just a shifted version of itself or the result of the ALU addition. So, when it takes the shifted version of itself it is like will regard it as if it is the adder is adding zero to it. So, in the case of shift and add will be passing this accumulators content through a one bit shifter and putting it at this adder and other input to the adder is going to be either x which is stored in this register x a clocked register either x or it could be zero. So, this will depend on whether we say the controller says shift and add. If the controller says only shift that means shift add add is zero then zero will be sent to this adder and then it will have this simply the effect of loading updating the accumulator with it shifted left shifted version. Note that this is not a shift register this is a simple shifter combinational shifter. So, in the inventory of data path very typically we require shifters combinational in general a barrel shifter is very useful component very efficient in general one uses barrel shifter a very important a typical component of useful data paths. Here we have a simple shift combinational shifter which is only shifting by one bit we also require a counter again a synchronous clock system whose output is being used like you know and which is being instructed which is being told which can be instructed to decrement and so on. And will be interested in seeing whether this count has reached zero or not sorry whether this count is zero or not zero checker we will use here count equal to zero. What else do we require this algorithm in the data path shift and add we will come back to it this looks like this is more or less what we require we require a controller now. So, controller for shift add a best multiplier so now again we see that we are very typically going to have one state in which the system will stay for long enough time knows what to do depending on the status signal generated by the by the data path itself the controller will use those status signal generated by data path and like decide on the control signals to be input to drive the data path again. So, looking at a status signal with the controller generates the control signals to the data path and that state I denoted by a typical state to do which is where the majority of the work is going to happen most of the cycle the system would stay in this state and what are the actions the outputs would depend on what the inputs are. So, the most important input to the controller is just we can see there is a control signal shift and add to decide whether to shift and add and anything else it will a lot will depend on whether the count is 0 or not as well as whether the we missed one thing MS the vice the shift register for y and this is the MSB and assume that this is the shift register. So, the MSB of y the most significant by a bit of the shift register is going to be of crucial importance and based on that actions will be decided if MSB of y is non-zero and if MSB of y is 0 these are the two possibilities if MSB of y is non-zero then the we are going to go back in this yeah actually we missed the important the important the count by whether count is equal to 0 or not you has even higher priorities. So, this will not work so quickly like from this state we check whether count is 0 or not if count is has dropped down to 0 we know that this computation is finished let us see what to do whether to go back to this state or not this is important this is when the computation continues if count is not 0 then it would depend on whether MSB is of y is non-zero or whether MSB of y is 0. If MSB of y is non-zero then we know that not only we have to shift, but also add x. So, we generate a certain control signal shift add to the data path we should also be decrementing the count right we should also be loading loading the accumulator with the result of the adder. So, enable accumulator to load itself and one more control signal will be shift y to left. So, all this control signals are asserted so that the multiplexer lets the x go through to the adder. So, that x is added with the shifted version of the accumulator and the result and count is decremented the result of the adder is loaded into the accumulator and y is shifted left. So, all this with the help of this control signals at the end of this current clock cycle appropriate data path operations data will happen and then we go back to this state. On the other hand if MSB of y is 0 then we only we do not shift and we do not add. So, which is like so it does not mean that we do not shift it simply means that we do not add. So, this signal is de asserted because we have decided to use a signal with the name shift add as the input is multiplexer. If shift add is 1 then we let x go through if shift add is 0 then we let 0 be added that means it has the effect of only shifting. So, shift add is de asserted when MSB is 0, but we still have to decrement counter decrement count enable the accumulator for loading and shift the y register register left by 1 bit and we go back to this state. Now, let us come to this particular situation when count was found to be 0. So, should we what are the control signals to be generators control or some output signals to be generated and this state we go to next. So, if like in the single state GCD controller if we are tempted to go back to this state then what would happen is that the computation would have been finished, but nothing would stop from this like shifting of accumulator and all that to happen because this system will keep reacting to might react to like the date what the value of y is MSB y with 0 or not might might in a change the contents of accumulator. So, which is what we do not desire. So, we want a system to freeze the freeze the results in the accumulator. In fact, fortunately that was not a concern in the single cycle because once y become 0 then even if swapping and even if that like subtract operation happens continues to happen x does not get changed because x minus y still happens to be the same as the old x. In this case like you know this accumulator contents might get shifted corrupted and so on. So, that is why we want the system to freeze when count becomes 0. So, we will go to us we will make the controller go to a state called state done and stay there until the next trigger. So, here I am just like just avoiding the role of the idle state and all that there is no I mean you know you can enhance this particular FSM with some more states for appropriate protocol of start triggering the computation of like indicating readiness of the result and so on. But essentially the main part core part of the FSM is this. Here I am just illustrating that I do not want I do not want to use the same state even when count becomes 0 because the count becomes 0 like you know go to the same state yeah I mean it is a simpler more typical approach of having a special state for indicating the end of computation. So, in this state all the signals would be set in such a value to such a value that the system would freeze accumulators would not accumulator would not change by register will not unnecessarily keep shifting and so on. So, quite typically I said we would like to have a state in which we when the control is in that state we know that system is the computation is done. So, when count becomes 0 we move to that state in which we can disable the accumulator from further change like loading it is loading something into itself we can also disable the counter. So, that it will remain at 0. So, that even if we have where to decide to go back here the count would have remained at 0 and so on. Or as a matter of test you might prefer a variation of this instead of this might feel that this could suffice as it is if count is not 0 it will depend on MSB y and a lot of this signals are specified here. If MSB is 0 then just shift do not add decrement counter enable accumulator and so on so forth what else shift y left and similarly here we go to this we go to this. If count were 0 then we might we might take a like you know we might prefer to use a single state machine of course, it will have some inedic faces, but it is not wrong or it like you know it can we can still make it work by like you know generating the control signals as follows we disable the accumulator we disable the counter. Once we disable the counter the count is going to stay at 0 and the system will keep moving in will keep doing this transition and would keep continue to keep the accumulator disabled continue to keep that counter disabled in which case we know that system would not escape into this count will not get modified to something count will not get updated to non-zero and dense based on MSB some accumulator loading or y shifting will happen. So, with the help of this kind of thing we this control signal values will ensure that system will loop harmlessly in this state with everything frozen effectively or if you prefer you might do that this particular way have a special state just a way we had a special state idle to indicate the beginning of computation waiting for some trigger we might we should also we could also have this this is more prefer we are doing it it is clearly if you are trying to be trying to make it purely combinational there should be some protocol problem not really problem, but something not so clean so should be a matter of so, so let us describe the data path in very log. So, this will also consolidate help consolidate understanding of how very log semantics capture the data path as well as the controller. So, the data path data path is synchronous system right. So, what is happening if let us let us make use of single cycle controller if count is not zero rather like. So, the logic for updatering updation of. So, after having seen the data path and is simple finite state machine based controller for shift add based multiplication we will just try to capture this in very log just to consolidate our understanding of how the semantics of very log and how the synthesis as a will map it into the circuit that we had drawn. So, let us first look at the this is the controller and let us look at a data path this is the data path what are the data storage components on the data path is an accumulator there is a register inside a counter which is being updated there are flip flops in the counter which are basically memory synchronous memory elements there is also a register x which is fortunately not getting updated may be if you have a start state idle I mean that is the time x will be loaded from the inputs and there is a shift register for y whose most significant bit is being named MSBY. So, we have to see what kind of actions are taking place on y accumulator and a counter. So, we capture this in very log. So, this is how it would look like always at this is the description of data path in very log always at positive edge of the clock that is a triggering edge of the clock. If the control signal says for enabling accumulator says yes that is they must be we assume that there is a control signal controlling whether the accumulator can be loaded or not we call it enable accumulator. If enable accumulator has been asserted by the controller then we would look at the output of the controller which is the control signal shift add if shift add is asserted is true then accumulator is to be loaded with shifted version of itself plus x. So, that means we have to compute the addition of the shifted version of accumulator and x and load it into accumulator that is this particular thing. If shift if this accumulator is to be loaded in this current clock cycle then it would depend on what the value of shift add is if this shift add is 1 then x is to be added with the shifted version of accumulator and loaded back into accumulator that is this particular statement. If enable accumulator if shift add then accumulator is loaded this way else accumulator is loaded only with the shifted version of itself. So, if shift add is 0 then 0 is routed to the adder nothing happens just the shifted version of the accumulator is routed back into the accumulator. So, it effectively means accumulator has been shifted by a single bit. So, that is the logic for how accumulator is updated. So, that is the logic in this particular block. Now, about the counter of course, this is not complete very log code, but main part of is this. If decrement counter signal is asserted by the controller then the counter will decrement otherwise counter will stay as its own at its own value it is like it will have the effect of disabling the counter. Similarly, the shift register is to be modified if is to be updated if the control signal shift y left is asserted then shift register is shifted left by 1 bit otherwise it stays. So, this shift y left is a signal say sent to this particular shift register shift add signal is generated by the controller and it is controlling this multiplexer enable accumulator signal is generated by the controller is controlling the loading of accumulator and decrement count another output of controller is controlling the counter. So, counter is also in part of the data path and it is being controlled by the FSM. Then this remains to understand how the controller would be generating the control signals which are those are the signals shift add enable accumulator shift y left and decrement count. So, it is the combinational logic for describing the output of controller initially these are the not is initial these are the default values which are going to be changed appropriately in the appropriate conditions. So, if the current state is state loop then if the count is not equal to 0 that means that is the main part of the loop then we will be shifting arranging to shift y will be decrementing the counter at the end of this clock cycle will also be enabling the accumulator for loading at the end of this clock cycle. So, all the signals are to be asserted and, but about shift add it would depend on whether MSB is y MSB y is non-zero if MSB y is 1 then we will be like you know performing addition of x to the shifted version of the accumulator that is controlled by the signal which is the input to the multiplexer else the shift add will be set to 0 which would mean that 0 will be sent to the adder and which will simply have the effect of only shifting the accumulator by 1 bit. In the state done we force this enable accumulator signal to be de asserted which means that accumulator will not be loaded whatever might be happening in the adder at the end of the at the output of the adder or somewhere else. Similarly, counter will not be will be frozen by setting decrement count to 0. So, counter will not be decrementing we hope that counter will also not be incrementing we will have we just assume that we have a specialist counter which only decrements or freezes. So, so on so forth. So, this is an always block describing the combinational logic for output logic of FSM which is combinational which depends on current state and the status inputs from the data path like whether count is 0 or not whether MSB of y is 0 or not right and we know that the signals are being generated whether count is equal to 0 or not is generated by taking the output of the counter and having a 0 checker MSB of y is taken directly from the most significant flip flop of shift register of this. So, this completes our description I mean this can be easily wrapped up in a module and some appropriate declarations of signals you as an exercise you might want to upgrade this controller. You might want to upgrade this controller like in the case of GCD to have an idle state to have a start trigger and to be able to load x new values of x input and y input into x and y. So, this is assuming that at like on reset itself we have something in x register and something in y register that is good enough only for testing, but as a subsystem you would need like you know appropriate input triggers. So, hope like typically you can make use of one state like state idle or state start then this is the main state and this is the ending state and from here again you will go back to that idle state waiting for a start trigger and so on. So, this can be like you know enhanced into more like better protocol for using a multiplier system that they just left us an exercise we have I try to illustrate the main points and I hope that should suffice.