 Hi friends this is Mowli here and welcome you all for the ninth session of the ARM based elephant course. In this session we will be touching upon addressing modes and once I say it is addressing mode means it is the data transfer instructions ok. So, far in the instruction set we have seen data processing part of it. Now we will be talking about data transfer instructions. So, you know that ARM is a risk processor and there are only two varieties of addressing sorry instruction which access the data they are load and stored ok. So, but ARM supports lots of different addressing modes which you can use it with those data transfer instructions. So, we will be covering here the first three modes in this session. Addressing mode one we will only see the examples because I have already talked about this in detail. Then we will go into mode two and three with little more details about what is happening inside the processor then these modes are activated by executing a specific instruction which belong to one of these modes. Now let us see first there are basically five addressing modes supported by ARM. The first mode is associated with the shift operands which are meant for data processing instructions or may be for any other load store instructions. So, once I say shifter operands that means it is the ARM ok. There are two operands ARM and ARM. We talk about ARM here the second operand which goes to the shifter barrel shifter in the instructions in the ARM processor and then these two are specifically meant for load store. The first one is for the word and unsigned byte ok. I will explain you and then this is about half word that is word means 32 bits half word is 16 bits and loading of signed byte ok. Then multiple store is also another feature supported by ARM we will be talking about this in the next session. And and load and coprocessor instructions we are not going to be talking about this instruction we are not going to be touching now. We will talk about this when we get to the coprocessor interface. Now addressing mode one ok. In this there are basically eleven formats different formats which we saw earlier. I will just to refresh your memory. I will give you one example of each and then we will we will go to the addressing mode two. Now generic instruction format is of course followed by the conditional code which decides whether this instruction has to be executed or not. And then yes if you add append to the instruction it means that whether this instruction can modify the CPSR of flags or not. And this is the destination register and ARM is one of the operands. And the ARM the second operand goes to the barrel shifter and we are going to talk about what all different ways we could modify the ARM operand for the instruction ok. Let us see an example a simple example is hash immediate that means we can mention an immediate constant. If you recall how many bits are supported for an immediate constant it is 12 bits ok. So, I can maximum write starting from yes yes yes 3 s ok into 4 12 bits. So, here this constant is coming along with the instruction and then that gets moved into r 0. If you recall move instruction is a single operand instruction. So, there is only one operand and then one ARM ok. This operand has to is happens to be ARM. And another single operand instruction which is the another single operand instruction MVM ok. If you remember we talked about that in the last class ok. Now, second format as I mentioned we are talking about what all we can do with the ARM here right the second operand may add instruction as two operands r 0 is equal to r 1 plus r 2. So, in this case the second operand is a straight forward a register ok. So, is there any operation done by the barrel shifter here for this register? No the value which comes from the register file goes to the shifter without any changes because it enters the ALU without any modification where you are not mentioned any shifting operations or rotating operation for this operand in this instruction ok. What is this EQ? You should be able to tell me write you know about this EQ is the conditional code which corresponds to whether 0 flag is set or not. If 0 flag is set prior to the execution of this instruction then this will be executed otherwise this instruction will be skipped ok. Now next example we are having a register ARM with a shift operator and a immediate constant. This is a logical shift left I have given an example here and this is a constant which is a 5 bit constant if you remember. So, a typical example could be this instruction. So, I am giving different kinds of instruction for you to understand when when you see such instructions you should be able to understand what is happening there because I am introducing only the instruction which you are already aware. So, before I explain this please remember this instruction is about ARM or Boolean arithmetic or operation and S is for saying that this instruction can support can affect the signal conditional flags in the processor and R 3 comma R 2. So, on R 2 what are we trying to do here? We are trying to do a logical shift left by 4 bits and then we are then we are moving after the shift logical shift left of the value in R 2 we are doing a Boolean arithmetic operation that is R operation Boolean R operation with the contents in R 3 and then the result is written into R 1. Now when I say that this flag X is here that means this instruction can modify the conditional flags after this instruction is executed. Now what are the flags will be affected by this? In any logical operations if you recall except the sign flag the 0 flag and the carry flag as well as the negative flags ok overflow flag will not be affected except that other 3 flags will be affected based on the result that is written into R 1 here. So, this is about logical operation with a shift operation ok it could be any other different operations could be mentioned. Now another type now if you say for here the shift operation was done based on the constant the 5 bit constant which was given along with the instruction. Now there is a possibility using this instruction we can always get a lower 8 bits of the register R 5 as the how many bits that need to be performed ok that operationlogical shift left by how many bits how many times that is given by the lower byte of the register mentioned here which is R 5 happens to be R 5. So, whatever is the lower byte in R 5 that many times this logical shift left will be done on the content of R 4 and that value is Boolean and will be done with R 3 and the result is written into R 1. But there are some conditions here this not equal to says that this instruction can be executed only when 0 flag is cleared prior to this execution and then S indicates that after this instruction in case if this instruction is executed if 0 flag was cleared and this instruction is executed then you will have the results of 3 flags except the overflow flag or the 3 flags will be affected by the value written into R ok. So, I hope now by now you should be clear about what is each instruction is doing. Now this is a other you should be able to find out the differences, but remain you know different formats there are minor changes, but you should be able to identify them. So, this 2 R LSL operations now you are see LSR that means, logical shift right. So, same thing what I explained for this is true here only thing is this many times the logical shift right is there that means, the bits are shifted to right and then the MSP part will be filled with 0s because it is a logical shift. Now all this you understand now MOV move it is actually moving the value from R 4 to R 1 after performing this operation on the content of R 4 into this. One more thing that you should remember in all of these operations whatever is the operands R n or R m the values of those operands are not disturbed by any of them ok. Only the R d the destination registers are modified and you are free to use any combination any kind of registers. In fact, you could use the same register in all the cases too those some in you know if you are using the R 15 which happens to be a program counter there are some restrictions other than that you will be able to use all the registers. If you really call the data part of beyond all the register contents are copied from the value. So, the shifting operation or whatever happened is not happened happening on the register itself the register values are copied and the barrel shifter is doing. So, please remember none of these registers operand registers will get modified because of executing this instruction. Only the R d will be modified provided this conditional codes are there if it satisfies this instruction is executed then R d will be changed and correspondingly based on whetheryou are doing the arithmetic operation or a logical operation. All the 4 flags will be affected if it is arithmetic operation except for the overflow flag other 3 flags will be affected if you are doing a move of boolean logical operations ok. This will I am summarizing this. So, I will not be explaining this again ok now let us go to the different mode LSR RS. So, same as LSR RS only thing is the shifting the how much of amount of shift needs to be done is taken from the register. If you see here the same register is used here. So, no issues what it will do whatever is the value of R 4 that many times the content of R 4 is shifted to the right logical shift is done by to the right and then that is move into R 1. But because it is MVN it is the negation of this particular value is done. That means, every bit isnow inverse of that bits are done and then the value is written into R 1. Now what is this condition MI is a condition code for minus. That means, if the sign flag is set that means, the it is a negative result is there because of the previous operation somewhere and then only this will be executed and based on based on this movement the any flags will be affected based on what is written into R. So, if you see you will see different instructions with a different names here based on what E 2 condition or any condition that you are choosing and then where you are using the S flag or not. So, you will have alots of varieties of instruction here. Now what is it you do here the similar to whatever L S L and L S R you call A S R is done is the arithmetic shift right that is bits are moved to the right and if sign flag is set it will be extended it all once will be coming in from the MSB side. Now this instruction is only thing I will explain you here P L is a plus that means, if the 0 the negative flag is not set that means, the previous result was a positive result and this will be executed. So, A S R with R S here you see I have chosen R 1 for everything. So, there is no issues ok there are no issues in doing this only thing is you should be aware that after the previous value whatever it was then R 1 is used by all this side of the instruction and then it is overwritten by this, but based on the condition whether the carry flag is C S is carry flag is set and then it will affect it will affect the flag and then subtract operation will be done that is R whatever is thehere this operand minus this whatever comes after this arithmetic shift ok. Now, R O R it is a rotate to the right that means, L S B bit comes back to MSB and R S B is what reverse subtract that means, instead of this operand minus this you do whatever comes after this operation that minus R 2 and then right into R 1 provided 0 flag is clear and it will affect the all the flags 4 flags because R S B is a arithmetic operation. Now, what is this R O R with a R S if the shift of how much of shift needs to be done rotation needs to be done is coming from another register and here again I have used all R 1 E O R is a X R operation. So, this operand and this operand X R will be done and the result is determined to this and provided carry flag is set R R X is a rotate extended that means, carry flag comes into MSB and the 0 flag goes into carry flag and compare instruction if it equal it does a comparison of these two values. In fact, effectively it will be subtracting it and then seeing whether all the flags will be set ok all the flags will be affected based on the result of this, but none of these operands get impacted because of this subtraction and it is done based on the condition. So, you can put any condition, but the S is not appearing here because it is default this compare instruction always affects the flags. So, even if you put S or more it does not matter it will compare instruction will always be affecting the flags. So, this summarizes the address mode 1 I intentionally took little more time to explain you every instruction. So, that it summarizes whatever you have seen so far. So, now, you are ready to use any of this instruction in different combinations to achieve whatever you have in mind. So, lots of things can be achieved because you have a whole lot of instructions at your disposal ok. Now, after this session you will have much more to operate on ok. So, let us now move over to addressing mode 2 ok. What does it do? It it supports I told you that it is a data transfer instruction that means, what this instruction help us in moving some value between a processor and a memory ok. And what this this mode what does it move? It moves a word that means, 32 bit word 32 bit value or a unsigned byte. So, it is very important remember I will explain with the example this is a unsigned byte which is moved across. Now, let us see what is the generic format task instruction? LDR is a load register this is store register. Load register means we are loading the register from the memory ok. So, it is moving some data from memory to a register execute it based on this condition. And store means what? You are moving some register content into your memory location. Now, B is optional because I told you that this instruction either moves a word this addressing modes support either moving a word or a byte that to unsigned byte. So, if you mention a B along with the instruction that means, LDR B if you say that means, you are interested in moving a byte ok. And then this part please ignore it for a moment because this will be clear only when exceptions are handled. So, during that time I will explain this. So, for a moment you can ignore this and then R D is a destination register. It could be the register which is getting the value from the memory or this is the register from which the value is written into the memory. Now, why are we calling this addressing mode? Because we are interested in moving how can I generate the address? Because when I say that it is something do the memory then you should know which part of the memory this instruction is supposed to access. And where it is supposed to write a word or a byte or where is it supposed to read a word or a byte? Now, it has to be this instruction should be given a proper address. Now, there are different ways this address can be generated. Why they are supported? I will explain on the way because it is to enable different kinds of support data structures support for the compiler this kind of different instructions are provided. So, what are the different ways you can generate an address is what we are going to talk about in this session ok. So, that is it about. Now, this is you do not have to memorize this this is only I am giving you just to be aware how a particular instruction is coded encoded in a 32 bit bit ok. Please remember all our instructions are 32 bit byte. So, any any kind of instruction you see they are all encoded into this particular 32 bit format. So, based on the particular instruction type the different kinds of flags or different kinds of bit positions are modified for the processors to understand that this is the kind of instruction coming from the memory ok. Now, if for addressing mode 2 this value will be 0 1 if if you remember the data processing instruction had a 0 0 there. So, processor will know as soon as it sees this it will know that ok is a addressing mode 2 instruction which is coming. So, based on this value it will decode the rest of the fields in the instruction. This already you are aware of it very what conditions on which it has to be executed. So, this is you already aware. Now, this bit also we have explained if it is 0 how to interpret the email constant if it is a 1 how to interpret it this also be addressed. So, immediate offset means it is a 12 bit value which I told you and earlier shift operation means a 5 bit value which can be here along with the RS value ok that we have already talked about. Now, these are the fields which are specific to the addressing mode. There are indexing bits free and post indexing bits and whether the address is going up or down or whether the offset is subtracted or add ok that is implicit here and whether we are transferring a word or a byte. I told you that this mode supports both a word transfer or an unsigned byte transfer. So, that is interpreted by using this bit position values a 0 or 1 and then this I will explain you this is about whether the address has to be written into the base register or not and whether you are doing a lower operation or slower operation is based on this ok. Now, I am mentioning a base register here ok when I show a typical example you will be very clear about it. Base register is the 1 of the 16 registers which are there in the processor whatever is the content of that is taken and then an offset value which is given here is either added or subtracted or it is rotated and then added any thing based on the type of the addressing mode. This offset is computed and added to the base register which is mentioned by this north value it could be anything from r 0 to r 15 and then at that address whatever is the content in the memory is either written into or read into this destination register ok. This is the simple explanation of this format ok. Let us go forward. Now, I am going to tell you how data part inside the ARM processor behaves ok. It is tied to the pipelining also. So, please pay very close attention to this. If you understand this pretty well then you will feel comfortable in you know understanding different instructions and you will be able to understand why certain things are happening the way it is ok. Now, I have given you a sequence of instructions here. What does it mean? By now you should be clear add I am just explaining the first two instruction add means r 1 plus r 2 which is written into r 0. Now, this you may you are seeing for the first time ok. So, for extending the data part I have to explain this ahead of the modes. So, please you know I will explain you what is it do so that you will be able to understand the data part. Now, what is this str means? It is a store instruction ok. What is it doing? It is storing something into the memory. Where is it taking the value? It is taking from the destination. It is called r d, but actually it is not a destination area for a store it is a source actually. So, this r 5 whatever is the content will actually write a word or a byte there is no b here ok. I am told you that if it is a b is written after str that means, it is a byte store, but it is a word store now ok. So, the whole 32 bit value of r 5 has to be written into some address. Now, where is the address what address processor does not know? So, we are giving the instruction to that saying that you take the value the 32 bit value what is there in hard to do ok and then you subtract it by minus 804. Why 804? You cannot give more than 3 hexadecimal value that means, 12 bits ok that is the limit. If you suppose if you give 1804 the somewhere will give a book error. So, when you put it into that a square bracket what does it mean? You compute this value ok take a value in R whatever is stored in R 2 and then subtract it from 804 and whatever the value get use that as a address. Send it to the memory and then write this value into it ok that is what is effectively you are informing the processor. Now, what is this exclamation mode? You are saying ok you are computing by doing this operation, but can I change this R 2 after this that is a optional one. If you mention exclamation mode that means, after this change you can overwrite the value in R 2 ok. You should I hope you understand this. So, if there is no exclamation mode it will be the value from R 2 is taken and then this is subtracted and that in that address the R 2 is stored, but it will not change the value of R 2 after the execution of the instruction. Whereas, if I put exclamation mark here it will after storing it it will always change the value in R 2 ok. So, that means, you are advancing the value that R 2 has by this much amount whenever this kind of instruction is executed. Now, this three other instructions are given just to explain a pipeline ok. Let us go into next stage now. Now, see here the first instruction is what you see here it is fetched here. When this instruction moves into decode the STR is fetched and when this STR goes into decode stage ok another add which is here this instruction is fetched. Now, during this time the processor is trying to understand what is given here. Now, it has to do so many things it has to first of all do this arithmetic, generate the address and then access the memory here to write the value in R 5 and then only it can move into next instruction. So, the execute stage of this instruction actually takes more than one cycle ok execution is still not complete until this is done. So, that is what I am trying to tell you what exactly is happening during this time. So, remember the decode stage always is in the pipeline right. So, decode stage generates the signals meant for the next stage. So, in this case it is for the calculation of address which is shown here ok and then it has to decode will be busy doing the control signal generation for transferring the data which will be shown in the next you know immediately after explaining this. So, that is why this decode logic is not if you see here decode is not shown at this particular time ok because this instruction decode is delayed that means, the decode is busy with the previous instruction ok in the pipeline that is why you see a gap here ok and then because of that what happens first calculation of address is done and then the transfer happens. So, remember the str instruction takes two cycles first ok to complete typical add instruction will do it will be completed within one cycle whereas, this takes two cycles. Now, let us try to see I am showing you this diagonal arm at this cycle ok during the calculation of the address. Now what I mean by calculating calculating the address it is to compute this. So, R 2 has to be at which is R 2 here R 2 is a base register ok because offset is added always to a base register we call it as a base register. So, in this case the R 2 is a base register where is it coming this is coming from here R 1. So, R 2 whatever is the content of R 2 is given to the ALU why are we using ALU because you are doing you are doing here arithmetic here based on whether plus or minus is given you will be either adding or subtracting this constant which is come along with a pipeline ok along with the instruction. This is is coming along with the instruction it is decoded into a 12 bit of value immediate constant which is coming along with the instruction that is why if there is a darkened path here what does it mean from the decode stage this constant 12 bit constant is coming to this pipeline register into the barrel shifter. Now you may wonder why is this L s and 0 here because you are not mentioned any shifter operation here you do not see any ROR or L s L or L s or ASR nothing is there. So, but the data has to go through the barrel shifter because it is the particular this data part is designed this way. So, any data coming in either through a register or through a pipeline that immediate constant it needs to pass through the barrel shifter. So, when there is no shift operation mentioned in the instruction the processor assumes it is a L s and 0 that is left shift logical shift left by 0 position what does it mean you are not modifying the value ok if you recall only L s L supports this hash 0 other operations like shift logical right or arithmetic right or ok right if you put 0 it means something different. So, that is why the logical left is decode encoded in the instruction as 0 0 and it is assumed here that it will be default set to 0 whenever it sees that there are no shift operation or rotate operation given along with the instruction. So, for this particular calculation there is no shift operation. So, now why is this coming through this I told you that this is the immediate constant which is coming along with the instruction when I say along with the instruction it is decoded it is part of the instruction it is encoded into that. So, it has been decoded by the decode stage and then if you pass on through the pipeline register and coming here you see here bit 12 bits are there 0 to 11 12 bits are shown here. So, that they come into this now this ALU has a option whether to perform a just take this value or do a A plus B or A minus B. Now, how will this ALU will be driven based on whether you have put a negative value or not this will do the job. So, now what happens in the algebra calculation R 2 is taken 804 comes through this without any shift and then it gets R 2 minus 804 is done by the ALU and then the computed value is going into the address register because you have written this whole thing into the square bracket that means, you are interested in accessing the address generated by this operation. So, that needs to go to address register. Now, you remember address register is common for both data access and instruction access because this supports a simply unified data and instruction memory the ARM 7 what we are talking about. So, because of this when any memory access is done this address register and the address bus this is tied to a address bus that will be address bus is used by the data access. That means, what it cannot perform a prefetch during this time that is why you see that during the calculation fetch is happening ok, but not during the access. So, so, what I mean by this is the address is a new calculator that means, that during that time the address register is already holding a PC no instruction address referring to this third this instruction forthnumber 4. So, it is accessing that instruction now and then once address calculation is done and it is overwritten into this address register then the next cycle it will not be doing a fetch that is why you see that there is no fetch here there is a gap. Please remember always in this particular data path ARM data path the address register holds the address for the next cycle what it is supposed to access. So, that is why during the calculation already this access is happening and this calculation is happening for computing the date address meant for the next cycle which is a data transfer because you are supposed to write some value into this address. So, it is calculated here and then actual accessing of memory is done in the next cycle. Now, there is something happening here what is it happening? You should be able to find out explain this yourself because I told you that address register was fetching a previous instruction prior to this. Now, next cycle is going to be taken over by by the data access that means, the address next address instruction address what needs to be fetched has to be saved back in the R 15 ok and it should be saved by implementing it by 4 and then writing into PC ok. So, the previous this address is incremented and kept in the PC. So, that next time it can be used for accessing the this instruction down that pipeline ok. So, that address is incremented and increment it is incremented by 4 remember and that gets written into PC ok. Now, this address register where all is it taking inputs from it is taking either from the increment or is it it is taking from the register file or it could come from the ALU. At one time only one of this input lines will be activated. So, that they drive the address into the register ok not these two are any two cannot be there right only one can be driving a particular value into the address register for the next access memory cycle. Similarly, during that time whatever is the previous content is taken and incremented and written into PC ok. I hope this whole thing is clear to you now ok. If you do not understand please listen to this explanation again or look at the diagram and this you will be able to make out what is happening ok. Shall we go to the next explanation next cycle what happens? So, please remember in this instruction there is a exclamation mark. So, we are supposed to write whatever the value you are accessing the offset you are added with R 2 you are supposed to write into R 2. Now, you may if suppose you are very critically evaluating this particular diagram you know trying to understand this you would have noticed that this is not enabled. That means, the offset after computing the new address it is not written into the R 2 immediately. It is done anyway this execute cycle is with the same instruction ok. It is it can be done in the next cycle, but why is it delayed? I will give a slight explanation now, but it will be clear when I talk about the data abort. See the processor is generating the address with the hope that the memory will provide the data or will allow the writing of the data into the memory. So, if suppose if the writing into the memory does not happen and data abort then memory will give a data abort signal back to the processor saying that hey this address is not valid you have to take some you know corrective action before executing this instruction. So, one abort signal will come. If suppose assume because the instruction says I need to modify the value of R 2 ok after this offset is computed offset is added with the base register. If it has written into the R 2 the old value of R 2 is now over ok. Now, suppose data abort happens now processor has to restart this instruction after the corrective action is stated. I will explain you what is the corrective action later, but somehow assume the processor can start the same SDR instruction again when it encounters the data abort. In that case what it what will happen? The R 2 would have been already updated then you would not be doing what you wanted to do right the processor would not be doing what you intend to do that is why until the memory cycle is completed this register is not modified. So, it says I want to know overwrite the value it waits for the memory cycle to do complete and the data to come from the memory or allowing the data to be written into the memory without any issue then in the next cycle once the transfer is then successfully then you can know easily update the value. Now, it is not that easy the processor architecture should support it because ALU should hold the value what it is computed now. So, that it can be used for writing into the register in the next cycle. So, I am just telling you why this is not cleared out. So, it directly write into this, but it does not write into the register part ok. I hope this is very clear to you now let us move on to next cycle. I have taken only this instruction which is of interest to us ok now pipeline is explained understood. Now if you remember in this cycle what happens the data transfer has what is this instruction it is supposed to be doing the next flow. That means, this r psi has to be written into the memory then this r psi has to go out to the data bus how does it go r psi is taken from this this part is taken. So, the decode logic is doing all the controls. So, that this part is activated now the whole word goes out ok at this moment I will explain you this also. If there was a STR byte it is supposed to only take a the byte value ok based on which byte you want to write. So, it is always when you say byte from the register it will always take the lower byte of the register, but based on the address generated it may have to be written into one of the four locations ok. So, I will explain you what I mean by one of the four locations suppose this is the ok this is 1000 I always take 1000 because it is easy to understand. So, this is the lower byte 0, 1001, 1002, 1003. Now suppose the address what you have generated has resulted in one of the values ok it could be 1001 or 2 or 3 and you have written a b here then what happens that particular ls byte from R5 ok has to be written into a particular byte of the in the memory. So, the memory could be you know because if you remember this ARM processor is a can be integrated with the any memory right. So, what is done by this unit is it will replicate the value in all of them all the bytes and then write into the generate that value into the data numbers. Suppose you are writing 5 that 5 is written into each of the bytes ok. Now you may wonder why is it you want to write know all 5 5's into the values no the memory is supposed to only write one byte based on the address what is generated in that location only, but it is given a flexibility that if it wants it can pick the byte from directly from this byte or this or this or anything ok. It depends on the way memory is interface that is the job done by this byte. So, this question mark is given provided if it is a byte access this will get activated and then the ls byte will be taken and then replicated in all the data buses data buses from B 0 to B 31 right. So, it will write the same byte value into all this position and give it to the memory can decide to do based on the address which is coming out of here. So, the address whatever 1000 1 or 2 will come out through this and data will go out through this. So, these are the data bus and address bus ok. I hope this is clear to you. Now let us see what happens I will explain some more things I have explained this part of it R 5 goes out and into the data bus and I told you that ALU is holding the previous computed value in in in its internal register and then writing into the where is it writing it is writing into R 2. Now R 2 is modified because there is a exclamation mark. So, that address is written into and the value is also the byte value or a word value is written to the memory also ok. It is completed now the data transfer has been done now. So, it is free to modify the register here. Now what is happening here? I told you when this data transfer is happening it has to generate an address for the next cycle because it has to do a prefetch. It has earlier saved that value into the PC now it goes out here into the address register. So, that now it can access the program the next value because the next cycle they say anyway this instruction is coming out of the execute state. So, the preview see next instruction will come into the execute state and the address access will happen now ok. So, the instruction the next instruction address is calling out from the PC that is why it was saved earlier and then now taken out from this. Please remember this value whatever is then address is overwritten by the you know address calculated by this the previous PC value would have been gone. So, that has to be kept there in the PC that is why it is done this way ok. I hope this is very clear to you. Now let us see I explained the whole thing with a load now what sorry stored now what happens with the load with the explanation so far you should be able to deduce what happens in the load. What will happen let us see suppose it was a load this will be same because computing the address is same ok. Now you can you can instead of saying stored you are saying that you compute the value address and then give me the word in that address and copy it into R 5 ok for a moment assume that it is in LDR. Now this you has to something has to be different here this will be same, but something has to be this here different what if this needs to be this will be same ok. They are writing the new value into the register will happen anyway, but instead of now driving the data bus with the value in R 5 you are going to take the data in because you are loading loading from memory to a register. So, this will be opened up. So, the data which comes in from the memory will come through this and now you would you see there is no way it can get into the register now right it cannot go in any other part. So, it has to come through the shifter and then it can into this value ok. So, so that is the way a load a data in happens for load. Now you have a problem now I told you this particular part is used for writing the address correct. Now I am saying that data also has to go through this it cannot happen together now with the catch understand this. When a particular value is loaded from memory in that cycle the value comes and sits in data in it is not taken inside because there is first of all there will be a delay of introducing so much ok if it has to be done in a clock. Another reason being this part is already used for writing back in case if there was a write back instruction. So, storing happens in the another cycle. So, we compare to store the LDR takes one more cycle to complete again you know let me explain again if I not followed I am telling that instead of STR LDR is there what does it mean you compute the offset and then access the memory in that address and store that value into R5. Now the computing the address is done by this cycle and in the data transfer cycle that address is put already the data has come in. So, the data is from memory it has come into this register and it stays there during the time this value has to be written back that happens without any disturbance and then one more cycle is taken that time this data will come through this and there will not be any shift here and it will not take any input the ALU also will pass this value out and now it will be written into R5. So, the memory content coming from memory lands here and then goes through this and finally, lands into R5 till then this execution is not complete this instruction is not done until the value from memory goes into R5. So, that is done. So, this actually completes the transfer ok. Now that is why I have put some note here it will take one more cycle you can read to LDR in sections follow a similar pattern except that the data from memory only gets as far as in data in register on the second cycle and the third cycle is needed to transfer the data from there to destination register. So, from here to destination register will be one more cycle if it was a LDR ok. I think once you understand this the rest of the part of the presentation will be a different ways of using the instruction. Now, let us see one by one I told you LDR or LDRB or LSTR or LSTRB based on right. Now there is a first mode which is called LDRSTR conditional flag B and expression what is it mean I will give an example. See here you have to pay little attention that dot data ok this dot data is a assembler syntax to say that it is a data segment. That means, you are declaring a data. Now num 1 is a some variable I have given I have declared it as a word and then writing it a 1, 2, 3, 4 initializing it. That means, before the program is loaded the assembler and the linker loaded takes care of particular location it allocates for num 1 variable and then loads this value 1, 2, 3, 4 in between it. Assume it happens to be a 1, 0, 1, 8 this is address ok allocated to that. So, it is there a prior to that condition there is also I am making sure that an ABCD is stored in the memory. So, this I am showing a memory contents of 32 bit write. So, 1, 2, 3, 4 is only occupied 16 bit that is why you see that there are 0s here. I think this will be very clear to you. Now, I am having an instruction called LDR same load R 3 equal to num 1. If I give this particular instruction what am I trying to do here? I am trying to see when I am declaring a variable of num 1. If I want to use that in my rigid in a inside my program I will not be able to use it until I know the address where it is stored ok. So, it has to be loaded that address at which the num 1 is declared assembler linker loader has done the job, but now I want to get the address this is the instruction used. Now, how is it done? When I say this the address of num 1 is written move into R 3. How is it computed? It is internally done by the this instruction is changed in such a way that a PC value whatever is the current PC value PC is what the R 15 is modified it is taken PC is not modified, but the only the PC value is taken and then some offset is added to that it is a PC relative addressing. What I mean by that? When this num 1 is there in the program it should be within the range of plus or minus 32 megabytes ok, because 12 bit offset and you know there is a detailed explanation that for that, but for now you remember that you understand that this particular variable will be in some range within the range of some existing PC value. So, what is the difference between that? The assembler can deduce it based on the current PC value because it knows where it is placing this program into the memory, but it knows that where the data is placed. So, it will accordingly place it in such a way that it can be accessed with respect to the PC. So, this instruction will inform the processor you take the PC value now add some offset which is given by this instruction and then you will get the address of num 1 here ok. So, that is what is done by this lower LDR instruction. Now, what does this do? You can do the same thing for not only for getting the address of any data variable in your program, you can also get a address of a label. See now in a typical assembly program you can always write some label a alphanumeric value followed by a colon. That means, this is the instruction and this is the label for that instruction. Now, where is this particular instruction stored? It is stored from the current PC of this instruction plus 4. So, it is very easy for this instruction to inform ok to conclude the value of label and then right now it is moved into PC itself. That means, what happens whatever is address here is moved into PC. So, effectively now PC will be moved to this register where to this particular instruction. You may wonder that ok anyway it may fall through also it will come here, but there is a minor difference between these two. When I move a new PC value the pipeline is flushed and then again started accessing from this instruction. So, there will be a minor performance change, but I am just explaining this for you to realize that how a label also can be given as a another parameter to the LDR instruction which is the this type of instruction and then you can get the value also you can write into any register or you can write into PC itself. That means, it will move to that particular value. Please remember you can write into PC only the program address because here a label actually points to a program address. You cannot put PC comma equal to num 1 it is a data some data you have stored not a actual this is not holding any program. So, if you do that you will have a problem and sometime assembler also is intelligent to given error ok. But be careful when you are modifying this values, but you should try to try this out in your simulator and understand what is happening ok. So, these are the values of new R 3 because num 1 is stored here. So, R 3 will be having this value and R 15 will be address of move instruction ok. Now, now tell me what is happening here. When I say this anyway num 1 whatever is where is the value is 1 8 it is plus 4 is done and that is move it to R 3 that is why R 3 will be 1 3 and R 15 I have this intentionally changed instead of PC I am making it R 15 just to know make it clear to you that it could be anything you can mention it as PC or R 15 and when I say label minus 4 label is the next instruction minus 4 is this instruction itself. So, when you execute this instruction PC will keep loaded with the same instruction. So, you will see that in the simulator it will keep executing this instruction you do not move forward it will not go anywhere it will be it will be ok. So, this will be address of this instruction is actually minus 4 and set 4 is this one. So, you have the same instruction. So, this is the first instruction let us go on to the next one like this this is the instruction