 So, let's go to the WL architecture and peripherals. I will show you only the data approach. So, the new peripherals, the new configurations, the new features. So, the key learning of that part is the WL architecture, the new peripherals and low power modes and low power features. WL embeds dual CPUs. So, we have Cortex-M4, Cortex-M0+, and it's important to remember that Cortex-M4 is more application MCU and the associated number is one. So, the CPU-1 means Cortex-M4 and Cortex-M0+, it is CPU-2. And CPU-2 is more related to the security area. What is important, we have three independent systems inside the WL. Cortex-M4, M0 and N-Radio can operate in independent way. This is the architecture of the dual core. So, we have three systems, CPU-1, CPU-2 and radio subsystem. There is common domain, which is relevant to all the cores. And in common domain, we have Flash, SRAM, One and Two, Reset and Clock Controller, Power Peripherial and External Interrupts Peripherial. And if NF Core is working, I mean N4 or M0, those peripherals are always clocked. And there are other peripherals in common domain, enabled per CPU. So, Inter-Processor Communication Controller, SEMaforce, AESP, PKI, some PKI Accelerator, Random, Number Generator, Trout Zone, Common Flash Interface and Sub-Eagle Heards Radio. So, Sub-Eagle Heards Radio can be, for example, assigned to Cortex-M0 or Cortex-M4. And within the domain of CPU-1, we have standard peripherals, well known from the STM32-L4 family. What you can see here also, the secure peripherals are marked in red. So, you can see here the AES, Random Number Generator, PKI, Trout Zone and Trout Zone Interrupts Controller. We can partially secure some peripherals, like Flash Memory, like SRAM, so we can isolate part of the flash, part of the SRAM, as secure one. Some peripherals are security aware, like DMH on us. It is important to remember that the radio system is Autonomous. So, we have Dual-Core system and the Flash and SRAM is shared between two cores. And for Cortex-M0, as a secure engine, a secure core, we can enable memory and peripheral isolations. Regarding HSE clock, the frequency is fixed, it is 32 MHz and this oscillator supports also TCX, also temperature compensated oscillator. The main reason for that is the support of Zick-Fox Modulation, but I will provide more details later on. We have two cores, so to allow the debug processing efficiently, so we have Debug Cross Trigger Unit. Debug Cross Trigger Unit, it is the peripheral, which allows to synchronize, for example, the breakpoints between both cores. For example, we can stop the application on both cores in the same time. We have integrated switching mode power supply in order to increase the power supply efficiency, to reduce the current consumption in run mode. More details later on. And for SNPS, we have dedicated pins, as you can see, those pins are diagonal of the radio pins. It is important in terms of reducing the noise impact of SNPS, especially to the radio receiver. And of course, this is QFP, the PGA package is also equipped with the same dedicated pins, placed in the same safe way from EMC point of view. More details about transceiver. The transceiver covers quite a wide band, starting from 150 MHz up to 960 MHz. And what is important within this band? We can cover not only the ISM band 433 MHz and A168-915, but also the wireless Mbass subband 169 MHz. For this band, the maximum allowed power is up to 500 MW. And thanks to this, the communication range can be quite significant for the FSK modulation. The basic functionality of the transceiver, it is of course the support of the Lora modulation from, let's say, several bits per second up to 17.4 kilobits per second. Support of GFSK modulation, so it is for example wireless Mbass or proprietary radio system. GMSK modulation, this is the subset of the FSK modulation, in fact. And it supports DPSK modulation, so binary phase shift keying. It is the modulation of ZIGFOX uplink. So the transceiver supports ZIGFOX. You will see during the last part of this workshop, the Lora 1 and ZIGFOX demo. Then oscillator, so we have external oscillator. It can be both crystal oscillator and TCXO. And internal RF PLL frequency source. This RF PLL is the basic circuit to generate the base frequency for transceiver. Then the transceiver provides the ultra power features, for example in standby. It is about 110 nano amps. The communication between the system and the transceiver is implemented through the SPI. This SPI interface is internal one. No externally exposed pins of that interface. There is a set of the radio interrupts to wake up the course. Radio can operate as an autonomous system. And thanks to this feature, it can wake up the course. And maximum output power is up to 22 dBms. And of course the external power amplifier can be connected. And regarding the IP of the transceiver, it is SEMTECH Hall. And it has been migrated from the combination of SEMTECH SX 1261 and SEMTECH 1262. So this is not direct migration from certain part number. Of the SEMTECH transceiver, it is a combination of 1261 and 1262. Considering that, I have practical hint for you. Because you can find questions regarding the crystals selections. Because the TCXO, it is not always the case due to costs. So there is dedicated application notes on SEMTECH website, the crystal selection guide. And in order to select properly the crystals for the WL transceiver, customers and you can based on the SX 1261 crystals suggested by SEMTECH. So the typical error of the bomb covers the balloon. Because the input of the receiver is a symmetrical one. So we need to unbalance the signal. Then we have matching network both for the RX and the TX path. In fact, this is low pass or band pass filter. Then we have antenna switch. And this switch, it is important. This is mandatory. The main reason for that is the radio performance, the sensitivity of the transceiver. The last part, it is antenna matching circuit. If antenna impedance is different than 50 ohms. Antenna part. So antenna, of course, can be PCB antenna. It can be ceramic antenna. It can be deep hole antenna. Depends on application. And oscillator, as I mentioned, ZIGFox TCXO is mandatory. Because ZIGFox means extremely narrow band modulation. VPSK modulation and crystal. But following the recommendation of SEMTECH, it is an option for Lora. For the crystal selection guide from SEMTECH, I mean AN-1200.14. It was the bomb regarding the radio path. And if you would like to decrease the current consumption in run mode, the SNPS is the point. And for that, we need extra coil. Important slide. So the finite state machine of transceiver. So after startup, after cold start, we are in sleep. And for sleep, the current consumption is about 50 nano ohms. Then if it is cold start, we need calibration. And then we are entering standby and standby is 110 nano ohms. As I remember well, the numbers are in data sheets. Always after standby, we need to enter FS stage. FS stage means frequency synthesis. And then if frequency is proper one, we can transmit. Then switch to the reception, or we can receive. And then switch to the transmission. And come back to the standby state. This FS stage is associated with particular timing. And this timing you can find in datasheet. It is between 300 and 400 microseconds. Of course, the calibration time is also defined. And the transition time between TX and RX is also defined. It's also defined. This timing is important in terms of the current consumption, of course, for the low power applications. So the data buffer, we have 256 bytes of RAM reserved for the data buffer. We have two separated buffers, TX buffer and RX buffer. And each buffer is associated with three parameters. So the base address, the buffer pointer, so the current pointer to the buffer and the payload length. Fortunately, thanks to the library, there is no need to care so much about the details because we have dedicated functions within the library. So we can just read or write to this buffer. Power supply. At first touch, the power supply looks quite complex. In fact, it is not so complicated. We need just to consider additional system. The radio system needs power supply. And we also need to consider the presence of the SMPS. So the main power supply domain, it is the VDD. Then we have analog peripherals like comparators, ADC, DAC, IRF buffer. We have power supply for the SMPS. And here, in fact, the SMPS, this is an output. This is the voltage generated by SMPS. Or if it is not active, it is the voltage generated by internal LDO. And this voltage is fixed. It's 1.5 volts, 1.55 in fact. We have also the dedicated pin for the radio part, VDD RF. And we have VBAT. So all the power supply domains except the radio are exactly the same like for SCM32L4 family. This slide has been presented already during the marketing part. I would like to highlight few points here. The first point is that the numbers are defined for the single core solution. So in fact, we can see the numbers from Cortex M4, SCM32L4 micro. The nice looking numbers, 71 micro amp per meter hertz and 100 micro amp per meter hertz for run mode are defined for the SMPS. And the numbers are defined when RF is off. The core mark score is 162. And please remember, there is no floating point implementation on Cortex M4. The current consumption numbers given within the datasheet are relevant to cores, so are core wise. For example, current consumption in stock mode. And the overall current consumption, it is the combination of the active core. So for example, Cortex M4 plus the current consumption of radio. So we have three independent subsystems. So when the at least one core is active, you can see in green the always clocked peripherals. Sub-GHz, power RCC and XTi, SRAM memory. And also you can see the security peripherals. So all the communication between the cores is possible thanks to the shared bus matrix. Both CPUs can enter the particular low power mode or power mode like SRAM, C-slip, C-stop independent way. And this is very important. It is possible to allocate the particular peripheral to particular CPU by using the dedicated bits in RCC registers. And it is also possible to allocate peripheral to both CPUs. Regarding low power modes, each CPU can decide independently which system low power modes can be used. Because of the STM32L4, we have well known low power modes like stop zero, stop one, stop two, stand by or shutdown. We can wake up each CPU independently, so we can assign the wake up source to each of the CPU. This is important because for dual core use case, if both CPUs wants to enter the low power mode, the hardware mechanism which is present on the top of the WL executes kind of compatible requests and it selects the highest low power mode which is compatible with the two requirements. What means the highest low power mode? It selects the highest current consumption low power mode. So, for example, if one CPU selects stop two and the second CPU selects stand by, this mechanism allows to enter stop two mode. And wake up is possible in independent way, so we can wake up, let's say, CPU one keeping the CPU two in low power mode. If we have two cores because of the security and both cores are in standby mode, during the wake up only the CPU one wakes up and the CPU two is still in reset mode in order to secure wake up. And the third system and low power mode behavior, so the sub gigahertz radio can also enter and exit low power mode in autonomous way. The radio can be woken up by both by the CPUs or by the low power timer. The sub gigahertz radio is independent, so it doesn't impact the CPU low power modes. And we can imagine the configuration when both cores are in low power mode and only the radio is active, so this way we can reduce the current consumption as much as possible and radio interrupt can wake up the selected CPU. So it is possible not only to wake up the system from stop mode by transceiver, but also from the standby mode, which is relevant to the lower one. Because we can imagine the configuration and the nodes transmits data every one day, so for such a configuration we can use standby mode. Of course the context must be stored in RAM memory because for standby mode the exit is through the reset procedure and just to remind you for the standby mode there is a possibility to preserve the for the data retention. So the SRAM tool has such a feature. SMPS, so adding SMPS the cost of the bomb is higher, but the power consumption efficiency is much better in RAM mode. So it makes sense for the systems where RAM mode is quite often. And as you can see for SMPS configuration we have power supply of the SMPS. So this is VDD SMPS pin. And then we have output from the SMPS regulator. And this is VFB SMPS and the output voltage is fixed. It is about 1.55 volts. And as you can see it is both input and output. So internally the main regulator and the low power regulator is connected to this domain. And externally we can use this voltage VFB SMPS to supply the VDD RF 1.5 volt power supply domain. So RF LDO here. And for LDO configuration we don't have a coil but the power consumption in RAM mode is higher. And of course the LDO configuration, this is practical hint, is much more relevant when we would like to really tune, really optimize the link budget because there is no noise generator here. So the reset and clock control peripheral I think quite well known having in mind STM32L4 family. The difference is that we have HSC fixed frequency so 32 megahertz crystal or TCXO. LSE, so this is standard clock for the RTC. In RTC LSI the implementation of LSI is quite nice because now LSI is fixed to 32 kilohertz and can act as a backup clock for the RTC. Of course LSI is used for the internal watchdog. Then we have MSI, HSI 16 megahertz and PLN. The maximum frequency of the system is up to 48. Megahertz and we have peripheral kernel clocks so because we need to clock the peripherals and well known feature from the L4 family the clocks can be dated. The slide you have seen to highlight the feature then we can allocate the CPU wise the peripheral we can allocate the peripheral to both CPUs so here you can see in blue you can see the peripheral allocated to the CPU one in orange to CPU two and in orange blue the peripheral which is allocated to both CPUs. We can then allocate peripherals just get the clocks of the peripherals in order to reduce the current consumption in round and slip mode and if at least one of the CPUs is active the peripherals in green are always clocked. TCXO interface so the TCXO is connected to the HSE oscillator so the HSE pins but TCXO needs power supply and the power supply is provided for TCXO it is so-called VDD TCXO it's provided using PB0 pin and this pin is multiplexed internally so the function of this pin can be PBZ, PB0 or the function can be VDD TCXO there is dedicated HSE bypass power bit in the RCC register to control the feature. LSI so internal oscillator low speed oscillator 32 kHz as I mentioned it can act as a backup clock for the RTC maybe as a main clock in order to reduce the the bomb cost and current consumption as well because LSI can be trimmed using timer 16 and HSE frequency as a time base and so if let's imagine the HSE is a TCXO so very good accuracy for example 2.5 BPM so we can use LSI as a main clock source for the RTC of course considering the periodic trimming and the current consumption is very nice so 110 Nm and again to highlight the radio operation is autonomous so a radio can operate without CPU and clocks for the radio systems are automatically enabled because there is internal 13 MHz clock and the activation of this clock is autonomous and automatic following the expected power state of the radio and that's all for the architecture