 Hello everyone, myself Sanjay Udge, Assistant Professor, Department of Electronics Engineering, Valchan Institute of Technology, Solapur. Today, we are going to discuss sequential logic circuits part one, learning outcome. At the end of this session, students will be able to analyze various sequential logic circuits. Outline, introduction, sequential logic circuits, asynchronous circuits, synchronous circuits, question, answer, flip-flops, references. Introduction, in combination logic circuits, output values depend on their present input values. Sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals, but on the sequence of past inputs, the input history as well. Input history is stored in the memory element. Sequential logic circuits, compute a function in a series of steps, use the result of one step as an input to the next circuit that can sample a value, a signal that says when to sample. Sequential logic circuit, this is the block diagram. Here, this is the conventional logic circuit having input and the output. Addition to this circuit, there is one more block shown as a memory block. This memory block has one input as the previous output from the combination logic circuit and another input which is called as clock signal, which is the train of clock rectangular pulses. The output of the memory is given or fed back to the combination logic circuit. So, sequential logic circuit is inherently contains a combination logic circuit as well as a memory element. The output will respond the input only when the memory will give the output. The memory will give the output signal only when the previous output is present and the most important clock is present. So, if the clock is absent, output of the memory will be absent, output of the final output sequential logic circuit will be absent. Digital sequential logic circuits are divided into synchronous and asynchronous types. In synchronous sequential circuits, the state of the device changes only at discrete times in response to a clock signal. In asynchronous circuits, the state of the device can change at any time in response to the changing input. So, it means synchronous type circuit requires a clock signal to change its output whereas, asynchronous doesn't require a clock signal to change the output. So, this is the main difference. Synchronous sequential logic. In a synchronous circuit, an electronic oscillator called a clock or clock generator generates a sequence of repetitive pulses called the clock signal which is distributed to all the memory elements in the circuit. The basic memory element in sequential logic is the flip clock. The output of each flip clock only changes when triggered by the clock's pulses. So, changes to the logic signals throughout the circuit all begins at the same time at regular intervals synchronous by the clock. A synchronous sequential logic. These circuits do not have clock circuit. When one event is completed, next event occurs. Such circuits have feedback path for finding internal state that is present output for generating successive output. A delay circuit or flip-flop is required for this purpose. The output of all the storage elements that is flip-flops in the circuit at any given time the binary data they contain is called the state of the circuit. This is the comparison between the conventional circuit and sequential circuit. So, a conventional circuit will have n number of inputs in response to the n number of inputs it will give n number of outputs. Whereas a sequential circuit it will it contains a conventional circuit having input and output but moreover it contains a memory block with memory block having one input that is the feedback from the previous output and the clock flip-flop. In electronics a flip-flop or latch is a circuit that has two stable states and can be used to store state information a biostable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. At the basic storage element in a sequential logic flip-flops and latches are fundamental building blocks of a digital electronics system used in computers, communications and many other types of systems. Flip-flop can be either level triggered a synchronous transparent or opaque or h triggered synchronous or clock. In level triggered the flip-flop can be triggered either at logic zero level or logic one level. H triggered means it is a flip-flop is triggered either going from zero to one or positive going h or negative going h. Flip-flops can be divided into common types the SR set reset d data or delay t toggle and jk flip-flops. The behavior of a particular type can be described by what is termed the characteristic equation which derives the next that is after the next clock pulse output q next that is the next output in terms of the input signals and or the current output. So this is the basic SR flip-flop have a built using four NAND gates. Clock let us consider that this clock will be always at logic one level. So s and r the two inputs q and q bar these are the two complement outputs. Let us consider the first case s zero r zero both are zero the according to the property of the NAND gate the output will be one only when the output must be when when the one of the two inputs is equals to zero. So that is NAND gate one and NAND gate two will have both outputs equals to one. Now let us assume that q is zero q bar is one so q is zero this zero is coming over here this is one so input to this NAND gate is one zero output is must be one this one going over here one one the output is zero it means that the previous state was zero one and the next is zero one it means that for SR flip-flop when s is equals to r is equals to zero there is no change in the output. Now let us consider this s is equals to one and r is equals to zero. So this r input is zero this must be one this must be zero so this is zero let us assume that this is zero and one this zero zero and one this one one zero zero and one this is one so when s is equals to one r equals to zero and the previous state is zero zero one the output will change to one zero so this is called as set state of the flip-flop next is the s zero r r one the output will change to q zero and q bar equals to one this is called as reset state. Now when s is equals to one and r equals to one when both the clock this this NAND gate will have one one this will also get one one so output will be zero zero these two NAND gates will have one input will be as zero so these they both will be try to become one which is prohibited okay. Next is the this is the symbol of a sr flip-flop this is the truth table what we discussed for s zero zero zero one zero one zero one zero one one this is a prohibited condition exercise assignment what is the drawback of sr flip-flop the answer is when both s is s and r are equals to one the output is prohibited okay the this condition is not allowed because all the for all the last two gates will try to become one output q and q bar will try to become one which is prohibited so this is the jk flip-flop the drawback of the sr flip-flop when s and r both equals to one is been eliminated in this jk flip-flop in the jk flip-flop which is similar to the sr flip-flop in which for both the j and k zero the output is no change jk one k zero output is one like a set condition j zero k one output is zero reset condition when j equals to one k equals to one output will tower that is q bar it means that for every clock pulse the output will change between one zero one zero one zero so this is the difference between the this so this is j and k flip-flop with j zero k k one j zero k one the q bar is one okay here now j is one and k is one the output is became one during the first clock pulse second clock pulse both one one output will now change to zero so in this way the output will tower this is the references thank you