 Hello and welcome to this presentation of the STM32F7 power controller. It covers efficient power management and all STM32F7 power modes. The STM32F7 has several key features related to power management. Efficient dynamic consumption with free running clocks gating when needed. This allows us to go down to 425 microamps per megahertz executing from flash memory. Independent power supplies allowing us to reduce MCU power consumption while some peripherals are supplied at higher voltages. And a battery backup domain called VBAT including the RTC and certain backup registers. The STM32F7 has several power supplies. The main power supply is VDD and supplies almost all the IOs except those mapped on dedicated supplies. In addition, VDD supplies the standby circuitry which includes the wake-up logic and independent watchdog. VDD supplies voltage regulators which provide the V-core supply. V-core supplies most of the digital peripherals and the SRAMs. The flash memory is supplied by both V-core and VDD. V-cap 1 and V-cap 2 pins have to be connected to external capacitors in regulator on mode. The exact value is specified in the datasheet. In regulator bypass mode the V-core supply can be provided externally on V-cap 1 and V-cap 2 pins. The value for the V-core is specified in the datasheet. The V-cap DSi pin has to be connected to external capacitors when the DSi regulator is available. The exact value is specified in the datasheet. Internal regulators providing V-core can also be bypassed and a 1.2 volt supply is provided by the V-cap pin in regulator off mode. Regulator on off mode is only available on packages with a bypass reg pin. STM32F7 microcontrollers feature several independent supplies for peripherals. VDDA for the analog peripherals, device PLLs and internal reset block. VDD and VDDA must be connected to the same source. VDDUSB for the USB transceiver. VDDSDMMC supplies 6 IOs used for SD card communication, SDMMC 2 clock, command and 4 data pins. The VDDDSi pin provides the DSi peripheral voltage supply. The VDDSDMMC and the VDDDSi pins are available only on some STM32F7 devices. The VRAF positive pin provides the reference voltage to the analog to digital and digital to analog converters. A backup battery can be connected to the VBAT pin to supply the backup domain. The main power supply VDD ensures full feature operation in all power modes from 1.7 up to 3.6 volts, allowing the microcontroller to be supplied by an external 1.8 volt regulator. Device functionality is guaranteed down to 1.7 volts when the internal reset is off. The analog power supply VDDA must be connected to VDD. When the analog to digital converter is used, VDDA voltage has an impact on its performance. VDDA must be greater than 2.4 volts for maximum ADC performance. The USB power supply or VDDUSB can be connected to any voltage other than VDD. When the USB is used, VDDUSB must be greater than 3 volts. GPIO pins PA11, PA12, PB14 and PB15 are supplied by VDDUSB. Six IOs corresponding to PF9 to PG12, PD6 and PD7 are supplied by VDDSDMMC independently from VDD. Several functions are available on these IOs, SDMMC2 in 4-bit mode, SP1 and I2S1. VDDSDMMC is available starting with packages that have at least 144 pins. A backup domain is supplied by VBAT, which must be greater than 1.65 volts. The backup domain contains the RTC, the 32.768 kHz LSE external oscillator and the 128-byte backup registers. VDDSDMMC is available only on some STM32F7 devices. It allows several IOs and functions, SDMMC2 in 4-bit mode, SPI1 or I2S1 to be used independently from VDD. IOs corresponding to PA11, PA12, PB14 and PB15 are supplied by VDDUSB independently from VDD. VDDUSB is used mainly as a USB transceiver supply when VDD is below 3 volts. Several functions are available on these IOs, USART1, USART4, SPI2 or I2S2. VDDDSI is available only on some STM32F7 packages embedding the DSI host peripheral. The VDDDSI pin provides the DSI host peripheral with a voltage supply ranging from 1.7 up to 3.6 volts. VCAPDSI is the DSI voltage regulator external capacitor. VDD12DSI is for the MIPI DSI-PHY supply, typical input voltage is 1.2 volts. The STM32F7 has an integrated POR-PDR circuitry that allows proper operation starting from 1.8 volts. The device remains in reset mode when VDD-VDDA is below a specified threshold without the need for an external reset circuit. The hysteresis between power on threshold and power off threshold is 40 millivolts. After reaching power on threshold for VDDA and VDD power supplies, the reset line is still kept low for a temporization time and then the reset line is released. The embedded internal reset controller monitors the VDD supply to detect if the supply is present or not and releases the reset signal when the supplied power reaches the threshold of 1.8 volts. The internal reset controller can be disabled by connecting the PDR on pin to VSS. When disabled it allows STM32 microcontrollers to operate down to 1.7 volts. On STM32F7 microcontrollers no external VDD power supervisor is needed to manage resets when the internal reset is off. In addition to power on reset functionality there is also a user configurable brownout reset or BOR unit which keeps the device under reset until the supply voltage reaches the specified VBOR threshold. BOR levels are configurable by option bytes. BOR off, BOR low, default, BOR medium and BOR high. VBOR is configured through device option bytes. By default BOR is off. 3 programmable VBOR threshold levels can be selected. BOR level 3 or VBOR 3. Brownout threshold level 3. BOR level 2 or VBOR 2. Brownout threshold level 2. And BOR level 1 or VBOR 1. Brownout threshold level 1. For full details about BOR characteristics refer to the electrical characteristics section in the device data sheet. This function is useful in applications where several devices have different operational voltage ranges. Depending on the BOR level the F7 microcontroller will not start until VDD voltage reaches the operational range of all connected devices. The programmable voltage detector or PVD is used to monitor the VDD power supply by comparing it to a threshold selected by software. An interrupt can be generated when VDD drops below the PVD threshold and or when VDD rises above the PVD threshold. PVD is internally connected to EXT I-Line 16. Depending on the STM32F7 device PVD interrupt can be connected to break input of timer 1 or timer 8 to put the timer's output signal in a safe configuration. This table describes the regulator on-off and internal reset on-off availability per package. For a list of available packages per STM32F7 line please refer to the data sheet. Two embedded linear voltage regulators supply all the digital circuitries except for the standby circuitry and the backup domain. A regulator output voltage or V-Core can be programmed by software to three different values depending on the performance and the power consumption requirements. This is called dynamic voltage scaling. Depending on the application mode V-Core is provided either by the main voltage regulator for run, sleep and stop modes or by the low power regulator for stop mode to optimize power consumption. The regulators are off in standby mode SRAMs and peripherals are powered down in standby. They must be reinitialized after exiting from this mode. The backup domain contains essentially the following blocks. The RTC unit and 128 bytes of RTC backup registers. Four kilobytes of backup SRAM. The LSE oscillator. PC13 to PC15 IOs plus PI8 IO when available. To retain the content of these blocks when VDD is turned off the VBAT pin can be connected to an optional battery providing a standby voltage supply. The switch to the VBAT supply is controlled by the power down reset embedded in the reset block. After reset the backup domain RTC registers RTC backup register and backup SRAM is protected against possible unwanted write accesses. Voltage scaling and overdrive mode offer flexibility between required performance and consumption. Overdrive mode allows the CPU and Core Logic to operate at higher frequencies than the normal mode for a given voltage scaling. In run mode three voltage scaling modes are available. Voltage scale one is the high performance range allowing a system clock up to 180 MHz. 216 MHz is possible with overdrive. Voltage scale two is the medium performance range allowing a system clock up to 168 MHz. 180 MHz is possible with overdrive. Voltage scale three is low performance and low power range that allows a system clock up to 144 MHz. Sleep mode allows all peripherals to be used and features the fastest wake up time. In this mode the CPU is stopped and each peripheral clock can be configured by software to be gated on or off during the sleep mode. This mode is entered by executing the assembler instruction wait for interrupt or wait for event. Depending on the sleep on exit bit configuration in the Cortex M7 system control register the MCU enters sleep mode as soon as the instruction is executed or as soon as it exits the lowest priority interrupt subroutine. This last configuration saves time and reduces consumption by eliminating the need to pop and push the stack. STM32F7 devices feature stop mode with different configurations to reduce leakage. Stop is the lowest power mode with full retention and only a 15 microsecond wake up time to run mode on HSI clock. The contents of SRAMs and all peripheral registers are preserved in stop mode. All high speed clocks are stopped. The 32.768 kHz external oscillator and 32 kHz internal oscillator can be enabled. Some peripherals can be active RTC and LP TIM. All EXT I-lines can wake up from stop mode. Wake up time depends on the power regulator and flash memory configuration. It can be in the range of 15 up to 120 microseconds. The system clock on wake up is the internal high speed oscillator running at 16 megahertz. Stop mode with underdrive mode enabled is the lowest power mode with full retention. Standby mode is the lowest power mode in which the 128 byte backup registers and 4 kilobyte backup SRAM are retained. The voltage regulator is in power down mode and the SRAMs and the peripheral registers are lost. As the V-Core domain is powered off, the ultra low power brownout reset is always on to ensure a safe reset regardless of the VDD slope. IOs are in high impedance state during standby mode. Six wake up pins are available to wake up the device from standby mode. The polarity of each wake up pin is configurable. The wake up from standby generates a system reset. Wake up time is 313 microseconds but the software initialization and configuration have to be taken into account as well. The backup domain allows us to keep the RTC functional and to preserve the backup registers in case the VDD supply is down thanks to a backup battery connected to the VBAT pin. The backup domain contains the RTC clocked by the low speed external oscillator at 32.768 kilohertz. Two tamper pins are functional in VBAT mode and erase the 128 byte backup registers also included in the VBAT domain in case of intrusion detection. The backup domain also contains the RTC configuration register. In case VDD drops below a certain threshold, the backup domain power supply automatically switches to VBAT. When VDD is back to normal, the backup domain power supply automatically switches back to VDD. This slide illustrates typical power consumption figures for the STM32F7 series. Typical value measurement conditions are room temperature, 25 degrees Celsius and VDD equals 3.3 volts. Dynamic run mode consumption is in the range of 425 microamps per megahertz while running core mark code from flash memory at maximum frequency. Stop low power mode with full retention for peripheral configuration and SRAMs is in the range of 130 microamps. For more details, you can refer to the datasheet. Two bits are available in the flash option bytes to prohibit entering a given low power mode. When cleared, these option bits trigger a reset when entering either standby or stop modes. This is a security feature used to reduce the impact of unintentional entry into these low power modes. In case these low power modes are not used in user code, the option should be enabled. Three bits are available in the debug control register in order to allow debugging in sleep, stop and standby modes. When the related bit is set, the regulator is kept on in standby mode and the HCLK and FCLK clocks remain on to keep the debugger active. This maintains the connection with the debugger during the low power modes and continues debugging after wake up. Remember to clear these bits when the MCU is not under debug because the consumption is higher in those low power modes when these bits are set due to the fact they force the clocks and the regulators to remain enabled.