 Hello and welcome to this presentation of the STM32 Octo-SPI interface that will present the features of this interface which is widely used to connect external memories to the microcontroller. Octo-SPI was first implemented in the STM32-L4 Plus. The version present in the STM32-L5 supports additional features. The Octo-SPI interface integrated inside STM32 products provides a communication interface allowing the microcontroller to communicate with external single, dual, quad or octal SPI memories. This interface is fully configurable allowing easy connection of any existing serial memories available today. The external device can be memory mapped which allows any system master to access it like internal memories for read and write operations. Applications will benefit from the easy connection of serial external memory with only a few pins required. Thanks to the memory mapping feature external memory could be simply accommodated in the existing project when more memory is needed whether it be flash or RAM. The Octo-SPI is a serial interface that enables communication with serial memories. The following protocols are supported. Serial flash, PS-RAM, Hyper-RAM and Hyper-Flash. The Octo-SPI always operates as a host controller. It initiates the data transferred to the memory. Two low-level protocols are implemented. Regular command mode which is an extension of quad SPI and hyper bus protocol. Three types of interfaces are supported. 8-bit, 4-bit and 2-times 4-bit. The Octo-SPI interface offers high flexibility for frame format configuration to address any serial flash from single data lane up to 8 data lines. As with regular quad SPI, the user can enable or disable each of the phases, configure the length of each phase and configure the number of lines used for each phase from 1 to 8. A new signal, RWDS, acts as either a write strobe during write operations or a read qualifier during read operations. This table summarizes the features of each transfer phase. The instruction phase transmits an instruction to the memory device specifying the type of operation to be performed. The address phase transmits the address of the operation. In the alternate bytes phase, 1 to 4 bytes are sent to the external device, generally to control the mode of operation. In the dummy cycles phase, 1 to 31 cycles are given without any data being sent or received in order to give the external device the time to prepare for the data phase when the higher clock frequencies are used. During the data phase, any number of bytes can be sent to or received from the external device. Any of these phases can be configured to be skipped, but at least one of the instruction, address, alternate byte, or data phases must be present. The Octo SPI supports the new HyperBus mode, which combines the command and addresses in a single initial phase. The HyperBus does not require any command specification nor any alternate bytes. As with the regular frame format, HyperBus mode also uses a read qualifier and a write strobe during the data operations. The Octo SPI supports variable or fixed external memory latency as defined by the HyperBus protocol specification. The HyperBus frame is composed of two phases, command address phase, data phase. This table summarizes the features of each of these phases. The command and address phase transmits both a command and an address to the memory device. 48 bits are transferred. Selecting the data transferred direction, the burst type, linear or wrap, the address space, memory or registers, and the address. During the data phase, any number of bytes can be sent to or received from the external device. Two timings have to be configured according to the characteristics of the HyperBus memory device. TRWR, which is the device read write recovery time, and TAC, which is the device's access time. If the device needs an additional latency, RWDS must be tied to one during the command address phase. The Octo SPI integrated inside STM32 products offers three operating modes, which will be explained later in this presentation. Communication with external memories supports single or dual data rate operation. The Octo SPI supports three different modes of operation. Indirect mode, where it behaves as a classical SPI interface and all operations are performed through registers. Status polling mode, where the flash status registers are read periodically with interrupt generation. Memory mapped mode, where external memory is seen as if it is internal memory for read operations. In indirect operating mode, the Octo SPI behaves like a classical SPI interface. Transferred data goes through the data register via a FIFO. Data exchange is driven by software or by the DMA using related interrupt flags in the Octo SPI status registers. Each command is launched by the writing of an instruction, address, or data depending on the instruction context. A specific mode has been implemented in the Octo SPI interface to autonomously poll status registers in the external flash. The Octo SPI interface can be configured to periodically read a register in the external flash. The return data can be masked to select the bits to be evaluated. The selected bits are compared with their required values stored in the match register. The result of the comparison can be treated in two ways. In ended mode, if all the selected bits match, an interrupt is generated. In ORD mode, if one of the selected bits matches, an interrupt is generated. When a match occurs, the Octo SPI interface can stop automatically. The Octo SPI also provides a memory mapped mode. The main application benefit introduced by this mode is the simple integration of an external memory extension with no difference between read or write accesses of internal or externally connected memory, except for the number of wait states. This mode is suitable for both read and write operations and external memories. Whether it be RAM or flash are seen as internal memory with wait states included to compensate for the lower speed of the external memory. The maximum size supported by this mode is limited to 256 megabyte. A prefetch buffer supports the local execution. Therefore, the code could be executed directly from the external memory without the need to download it into the internal RAM. This mode supports also a mode called send instruction only once mode known as SIOO, which is supported by some flash memories. It allows the controller to send instructions once only and remove the instruction phase for the following accesses. The Octo SPI has five interrupt sources. Timeout. Status match when the masked received data matches the corresponding bits in the match register in automatic polling mode. FIFO threshold. Transfer complete. And transfer error. DMA requests can be generated in indirect mode when the FIFO threshold has been reached. The Octo SPI is active in run, sleep, low power run and low power sleep mode. An Octo SPI interrupt can cause the device to exit sleep or low power sleep mode. In stop zero, stop one or stop two mode, the Octo SPI is frozen and its registers content is maintained. In standby or shutdown mode, the Octo SPI is powered down and it must be initialized afterward. Wearable applications are requiring low power management together with high quality HMI. This can be achieved using the STM32L5 Octo SPI interface to store in an external flash all the graphical content needed like background images, high resolution icons or fonts to support multiple languages. Additional audio data for ringtones can also benefit from the large space offered by the external flash. The low pin count needed to drive such devices allows a very optimized system integration. You can refer to peripheral training slides related to RCC, interrupts, DMA and GPIO for additional information. For more details, please have a look into the application note AN5050 about the Octo SPI interface.