 Hello and welcome to this presentation of the STM32L4 Digital to Analog Converter. All the features of this analog block will be presented, which are used to convert digital signals to analog voltages which can interface with the external world. The Digital to Analog Converter on STM32L products ensures the conversion of 8 or 12-bit digital data to the analog voltage. Two DAC modules are embedded in the STM32L4 devices, except on STM32L45X46X devices, where only one DAC is implemented. A low-power sample and hold mode is also integrated. The DAC can interface with external pots or bias circuitry. It can also create voice and arbitrary signals. The Digital to Analog Converter inside STM32L4 products offers simple digital to analog conversion in an 8 or 12-bit mode. 10-bit monotonicity is guaranteed. The DAC output can have a low impedance buffer to drive external loads. Its sample and hold mode can reduce power consumption significantly. Two DACs can be synchronized with each other. The input data can be transferred by DMA, which offloads the CPU. The DAC output data can be updated by a timer or an external trigger, as well as a software trigger. It also integrates small logic to generate noise waves as well as triangle waves. Here you can see the simplified block diagram of the Digital to Analog converter. The STM32L4 integrates two of them, except on STM32L45X46X devices, where only one DAC is implemented. The DAC output can be buffered for low impedance loads. When unbuffered, the output is directly connected to the R2R resistor ladder network type of DAC. The DAC can support different input formats. In 8-bit mode, it's a right aligned 8-bit data format. In dual channel mode, it's an 8-bit plus 8-bit data format in order to provide input data for two DACs simultaneously. In 12-bit mode, either a right or left aligned mode can be used for input data. DAC output conversion is started by writing to the data hold register by software. Six different timer outputs, an external I.O. or software can trigger the DAC conversion. The Digital to Analog converter has a sample and hold mode feature. The DAC can work intermittently, charge the external or internal capacitor, and be powered down while the output voltage is kept on the hold capacitor. After a certain period, the DAC is powered back on again and recharges the hold capacitor. By doing so, the DAC is only active during very low duty cycles, resulting in very low power consumption. The duty cycle program is very flexible and autonomous. The DAC digital interface integrates two special signal generators. The linear feedback shift register can create the noise signal for the DAC input. Each trigger updates the DAC output data by an LFSR block. The up-down counter with a programmable count value can create triangle wave data which can update the DAC output data. The data can also be updated by a trigger signal. The DAC can also create DMA requests from the trigger signal. Once a trigger is detected, the data hold register value is then transferred to the data output register. Then the DMA request is generated to obtain the new data for the data hold register. As the update of the output data register is initiated directly by the trigger signal, the DAC output signal will not have jitter, so that it can create a stable sampling time signal output, making it easy to filter out the sampling frequency. The DAC can generate a DMA underrun interrupt. To transfer data from memory, a DMA request can be generated. The digital to analog converter is active in the following low power modes. Run, sleep, low power run, low power sleep, stop 0 and stop 1. In stop 2 mode, the DAC is not available, but the content of its registers is kept. In standby or shutdown modes, the DAC is powered down and it must be re-initialized afterwards. The following table shows some performance parameters for the digital to analog converter. The DAC can work between 1.8 and 3.6 volts. 10-bit monotonicity is guaranteed. Power consumption is 185 microamps when the buffer is enabled and 155 microamps when the buffer is disabled. By using sample and hold mode, the current consumption can be drastically reduced. Depending on the condition and the hold capacitor characteristics, less than 1 microamp current consumption is possible for this mode. The DAC buffered output has a settling time of 1.8 microseconds with 5 kilo ohms and 50 pf load. The DAC can handle a sampling rate of 1 mega-sample per second. When using external components, it can support up to 10 mega-samples per second. This is described in detail in application note AN-4566. This is a list of peripherals related to the DAC. Please refer to these peripheral trainings for more information if needed. Application notes dedicated to DAC topics are also available.