 The following slides present an overview of the architecture of the new variants of the STM32H7 family. The schematic shows the architecture of the STM32H7273 lines. The main differences with STM32H7475 microcontrollers are highlighted in red. Only one bank flash is available compared to the dual bank flash of STM32H7475 lines. Two octo-SPI interfaces support most of the serial external memories. The on-the-fly decryption engine, available in crypto devices, STM32H73 allows the on-the-fly decryption of encrypted content that is then stored in external octo-SPI memories. The STM32H7273 offers 192 kilobytes of RAM split in three 64 kilobyte blocks. Those blocks can be connected either to AXI or ITCM. More explanations on STM32H72737475 architecture and performance are available in application note AN4891. The size of the RAMs are globally decreased compared to the STM32H7475 line. To increase processing performance, the size of both data and instruction caches have been increased from 16 kilobytes to 32 kilobytes. Thanks to the shared RAM, the ITCM, accessible at CPU max frequency, can be increased from 64 kilobytes to 128, 192, or 256 kilobytes. Two accelerators have been added. The Cortic coprocessor accelerates certain mathematical functions, mainly trigonometric ones, and the FMAC accelerator performs arithmetic operation on vectors. The product is available with three different flash sizes, 1 megabyte, 512 kilobytes, and 128 kilobytes configuration. This and the following table show a comparison between the STM32H7273, STM32H7A7B, and STM32H7475 lines. The main differences are indicated in pink. When the internal temperature does not exceed 105 degrees Celsius, the CPU can run at a frequency up to 550 megahertz. At higher temperature, up to 140 degrees Celsius, the CPU can run up to 480 megahertz. To reach 550 megahertz, the LDO can be used in the same way as for STM32H7475 devices, but the STM32H7273 microcontrollers can also use the SMPS regulator instead to improve power efficiency. The STM32H7273 line has only one bank of flash. The total size of the RAMs connected to the AXI bus matrix can reach 320 kilobytes if the whole 192 kilobyte memory space shared with ITCM is dedicated to AXI RAM. The size reduction comparisons for the RAMs connected to the AHB bus matrix, located in D2 and D3 domain, are shown in this table. The RAM error code correction, ECC, is available on all L1 cache, TCM, AXI, and AHB RAM. Note that when the CPU is running above 520 megahertz, the ECC on TCM RAM needs to be disabled. STM32H7273 products also embed up to two octo-SPI interfaces. An IO manager supports the multiplexing of two external octo-SPI memories on a single memory interface. For STM32H73, information protection data can be stored encrypted in the external octo-SPI memory. When read, those data can be decrypted on the fly. The three power domains are kept identical to STM32H7475 devices. Two general-purpose 32-bit timers have been added. The specific high-resolution timer is no longer present, and only one SISTIC timer is present, resulting from the single CPU architecture. To enhance display and graphic features, TFT LCD controller and Chromart accelerator are still present. MIPI DSi and JPEG decoder are not available. One UART, one USART, one I2C, and one FD-KEN have been added. One I2S has been added to one SPI interface, and the Parallel Synchronous Slave Interface or PSSI feature has been added to the digital camera interface. The number of serial audio interfaces or SAIs has been reduced to two. One USB full-speed has been removed, keeping only one USB that can be configured in high-speed or full-speed mode. STM32H7273 devices embed the same two 16-bit analog to digital converters or ADCs located in D2 power domain. The ADC located in D3 domain has been replaced by a 12-bit ADC. The internal temperature can be measured thanks to a sensor connected by default to ADC3 or through a digital sensor to avoid the ADC usage. Two accelerators have been added. The Cordic Co-Processor accelerates certain mathematical functions, mainly trigonometric ones, and the FMAC accelerator performs arithmetic operations on vectors. The Random Number Generator, or RNG, is a NIST SP890B compliant entropy source. The two embedded on-the-fly decryption units, or OTF-deck, allow the on-the-fly decryption of content stored in external octo-SPI memories. The procedure to use encrypted data is described in a dedicated application note, AN5281. The OTF-deck feature is only available for STM32H73 crypto devices. The STM32H7273 are single CPU core devices, so only one independent watchdog and one window watchdog are included. The presentation shows in green the implementation of the IPs added to the STM32H7475 devices. They will be detailed in the next slides. The size of L1 data and instruction cache closely connected to the core have been doubled to 32 kilobytes. The ITCM size is flexible. On top of fixed 64 bytes, 192 kilobytes of RAM can be connected either to ITCM or AXIS RAM. The CPU and those close RAMs can run up to 550 MHz. The size of RAM dedicated to the debug trace is reduced from 4 kilobytes to 2 kilobytes. Only one flash memory bank is connected to the AXI matrix. Two slave ports of AXI matrix are used for octo-SPI instead of one for the quad-SPI on STM32H7475 devices. On crypto-STM32H73X devices, the octo-SPI is connected to AXI through the on-the-fly decryption or OTF-deck. It can be activated or not. In D2 domain, two 32-bit timers, one FD-CAN and one I2C, have been added on APB-1 bus. One USART and one UART have been added to APB-2 bus. The two accelerators, CORDIC and FMAC and the PSSI have been added to AHB-2 bus. In D3 domain, the 16-bit ADC has been replaced by a low-power 12-bit ADC. The SPI-6 now has an I2S feature included. The slide explains how to supply the device, the different possible configurations, the internal generated supplies and the different power modes. The STM32H7273 line has the same power supply scheme and power modes as the STM32H7475 line. The STM32H725735730 lines also embed a switch mode power supply or SMPS step-down converter to improve power efficiency. All STM32H72X73X devices embed a low drop output or LDO regulator, except for the 68-pin package, which embeds only the SMPS. To provide the core supply, several system supply configurations are available. The digital power can be supplied either by the internal linear voltage regulator, the embedded SMPS step-down converter, or directly by an external supply voltage in regulator bypass mode. The SMPS step-down converter can also be cascaded with the linear voltage regulator. It's important to connect the device according to these schematics, and to ensure a correct power-up of the device. For devices not supporting the SMPS feature, only the LDO regulator is available. In this case, two configurations are possible, and the VDD LDO regulator supply is directly provided through VDD without a dedicated package pin. The STM32H72X73 line domain usage of some power scale has been increased compared to STM32H7475 line. SMP use is available for VOS-0. In this domain, the CPU can reach its highest speed, which also means the highest dynamic current consumption. Using the SMPS instead of LDO reduces the power consumption. Reducing the power consumption helps reduce the internal temperature, which in turn reduces the internal leakage in a virtuous circle. In VOS-1, the SMPS can be used with a junction temperature up to 140 degrees Celsius, which is possible only from VOS-2 for STM32H75. It means that for this high temperature, the maximum CPU speed is 480 MHz for the STM32H72X73 line instead of 300 MHz for the STM32H75 line. SVOS-4 and SVOS-5 can be used at 125 degrees Celsius instead of 105 degrees Celsius, which eases the usage of those low power modes at high temperature. The maximum frequency in VOS-3 is decreased from 200 MHz to 170 MHz. This table shows typical consumption for LDO slash SMPS for voltage supply of 3.3 volts. Comparison of line 550 MHz and 480 MHz shows that STM32H7273 line reaches a higher performance with a slight consumption decrease using LDO. This becomes a huge decrease when using SMPS. Modifications regarding internal RAM memories and peripherals imply a modification of the memory mapping. Due to the presence in default mapping of OctoSPI-2 in place of FMC's SD-RAM Bank 1, the STM32H7273 line does not propose the remap of the FMC's SR-DRAM Bank 2. Only the FMC's SD-RAM Bank 1 can be remapped. Thank you.