 Hello and welcome to this presentation of the STM32 nested vectored interrupt controller called NVIC. We will be presenting the features of this controller. The interrupt controller belongs to the Cortex-M0 plus CPU enabling a close coupling with the processor core. The main features are 32 interrupt sources, 4 programmable priority levels, low latency exception and interrupt handling, automatic nesting, power management control. Applications can benefit from dynamic prioritization of the interrupt levels, fast response to the requests thanks to low latency responses and tail chaining, as well as from vector table relocation. The NVIC provides a fast response to interrupt requests, allowing an application to quickly serve incoming events. The ARM V6M limits to 32 the number of interrupt request inputs of the NVIC. However, the STM32G0 implements more interrupt events than 32. A separate unit called syscfg is in charge of combining several interrupts onto the same interrupt line. By reading the IT line registers in this syscfg module, software can quickly determine the peripheral that has requested the interrupt. The priority assigned to each interrupt request is programmable and can be dynamically changed. The interrupt vector table can also be relocated, which allows the system designer to adapt the placement of interrupt service routines to the application's memory layout. For instance, the vector table can be relocated in RAM. Software is in charge of assigning a priority level to each interrupt, as well as to all exception sources, not including reset, NMI and hard fault. Whenever a peripheral interrupt is requested at the same time as a supervisor call instruction is executed, the relative priority of these hardware and software exceptions will dictate which one will be taken first. Regarding the STM32G0, the NMI is caused by an SRAM parity error, a flash double ECC error or clock failure. The priority of any of the 32 peripheral interrupt requests is programmable in a dedicated priority field located in Cortex-M0 plus NVIC registers. The NVIC provides several features for efficient handling of exceptions. When an interrupt is served and a new request with higher priority arrives, the new exception can preempt the current one. This is called nested exception handling. The previous exception handler resumes execution after the higher priority exception is handled. A microcode present in the Cortex-M0 plus automatically pushes the context to the current stack and restores it upon interrupt's return. When an interrupt request with lower or equal priority is raised during execution of an interrupt handler, it becomes pending. Once the current interrupt handler is finished, the context saving and restoring process is skipped and control is transferred directly to the new exception handler to decrease interrupt latency. So back-to-back interrupts with decreasing priorities, higher priority values, are chained with a very short latency of a few clock cycles. When an interrupt arrives, the processor first saves the program context before executing the interrupt handler. If the processor is performing this context saving operation when an interrupt of higher priority arrives, the processor switches directly to handling the higher priority interrupt when it's finished saving the program context. Then, tail chaining will be used prior to executing the IRQB interrupt service routine. When all of the exception handlers have been run and no other exception is pending, the processor restores the previous context from the stack and returns to normal application execution. When accessing the NVIC registers, ensure that your code uses a correctly aligned register access. Unaligned access is not supported for NVIC registers as well as all memory mapped registers located in the Cortex N0+. An interrupt becomes pending when the source asks for service. Disabling the interrupt only prevents the processor from taking that interrupt. Make sure the related interrupt flag is cleared before enabling the interrupt vector. Before relocating the vector table using the VTOR register, ensure that fault handlers, NMI and all enabled interrupts are correctly set up on the new location. The NVIC is linked with the CIS CFG module and the Cortex M0 plus CPU. Please refer to the related presentations. For detailed information, please refer to the programming manual for the Cortex M0 plus core and the reference manual of the STM32G0.