 Hello everyone, this is Vaishwana Chavan, Assistant Professor, Department of Computer Science and Engineering, Walton Institute of Technology, Solapur. Now I am here to explain the Pipeline Schedule Optimization concept. So at the end of this session, the students will be able to illustrate the state diagram for a given function. So before focusing on Pipeline Schedule Optimization, we should know the term Grady Cycle and MAR, Minimum Average Latency. So the Grady Cycle is nothing but whose edges are all made with minimum latencies from their respective starting states, which is called Grady Cycle and the MAR, which is nothing but minimum average latency, which is at least one of the Grady Cycles, which leads to the minimal average latency. So bounce on the MAR. The MAR is lower bounded by maximum number of checkmarks in any row of reservation table and this is lower than or equal to the average latency of any Grady Cycle in the state diagram. The average latency of any Grady Cycle is upper bounded by the number of ones in the initial collision vector plus one. So this is also an upper bound on the MAR. Now we will see the term delay insertion. So this is the delay insertion, which is introduced based on the requirement for example, the purpose of delay insertion is to modify the reservation table, which yielding a new collision vector. This leads to a modified state diagram obviously, because once we get new collision vector, so there will be modification in state diagram, which may be produce Grady Cycles meeting the lower bound on the MAR. So this is the main objective to insert the delay. So we will see how delay can be inserted. Before that, now this is the three stage pipeline, which is having stages S1, S2 and S3, which is made up of three types of connections, feed forward, feedback and streamline connection. So here we are getting the output, which is say output X, which is delivered from function from stage S1. So this is the reservation table and the operations which are being delayed. Say along X axis, it indicates time, time slots T1 to T5 and along Y axis, it indicates the different stages, stage S1, S2, S3 like that and here X1, which is connected to next stage S2, S2, S3 next in T5, it is connected to S1. Now it is delayed by 1 clock cycle and this is delayed by 1 clock cycle D1, this is D2. So this is a new state transition diagram with the minimal average latency, which is equal to 3. So this is the initial collision vector 1, 0, 1, 1. So the third position is having 0 and hence we will receive the same state after third 3 times right shift to this and perform logical or between this initial collision vector and the value which we received after 3 bit right shift that gives the same value and hence it is indicated to the same state with 3 star. And after fifth, fifth onwards all 0 will be there if you are with this initial collision vector you will get same state and this is having the minimal average latency which is equal to 3. So this is nothing but at least one of the greedy cycles which leads to the MAR and the greedy cycle is nothing but whose edges are made with minimum latencies from their respective starting state which is 3 and hence the MAR is 3 for this new transition diagram. Now this is the insertion of two non-compute delay stages which is D1 and D2. So here the stages S1, S2 and S3 are there and these delays are going to introduce the new state, new state. So we will focus on the next state transition diagram which is drawn by considering the delay. So before that you answer for this question, what are the bounds determined by Shar on MAR, the name of the scientist. So what are the bounds? So pause this video and write your answer. I hope your answer for this, the answer is the MAR is lower bounded by the maximum number of check marks in any row of the reservation table and it is lower than or equal to the average latency of any greedy cycles in the state diagram and the third point, the average latency of any greedy cycle is upper bounded by the number of ones in the initial collision vector plus one. This is also the upper bound on the MAR. Now this is the modified reservation table by considering the delay. By considering the delay, now D1 and D2 they are introduced here. So here we are having different stages S1, S2, S3 and D1 and D2 delay are introduced and hence this is the new reservation table we form based on the introduction of delay as we saw it in previous diagram here. So this delay is going to lead the new collision vector, new collision vector. See here this is the modified state diagram by considering the introduction of delay. So this is the initial collision vector 1, 0, 0, 0, 1, 0 and based on this initial collision vector normally wherever we find 0 that particular position indicates that which is permissible and wherever we find 1 that indicates that there is a collision. Now we have to avoid the collision. So by based on the logic which we studied in previous video based on that now we are going to find the next states. So if you right shift this initial collision vector then we will get 0, right most position is 0 means after right shifting 1 bit position itself we get the permissible and hence the next state which is 1, 1, 0, 0, 1, 1. So which is received by oring the right shifted value with initial collision vector and hence this one is indicated here. Similarly after right shifting the next 3, 4, 5 we will come back to this state 3, this is for 4, this is for 5 then 6, 7th this is for 7 onwards so these are the ways with respect to this state. So 7 plus onwards we will get all 0s and hence we will get we will arrive to same stage. So if you consider this state 1, 2, 3, 4, 3 and 4 they are the outlets. So 3 which leads to next state this one, 4 which will come to this state and if you consider this state then 3, 4, 5 will be permissible 3 then this is 5, this is 4 and 7 onwards it will come here and 5 will come back. If you take this state then this is 1, then 4, 5, this is 1, this is 4 and this is 5 and after 7th we will come back to the same state. So this is how this diagram, the new diagram is found which is by introducing the delay. So based on that if you observe this diagram the ML minimal average latency that will be 1 plus 3 divided by 2. So here the minimum value 1 and 3, 1 plus 3 divided by 2 which is equal to 2 and hence the modified state diagram gives the ML is equal to 2. So if you observe this ML with respect to the previous ML, so previous was 3 now this is 2. So this indicates that there is an optimization in ML. So this is how the pipeline is scheduled for optimization by inserting delay. So these are the references, thank you.