 Hvala. Veselim, da se možete vzlušati. Vzlušam, da je ovo sestemboot in korboot, kaj je projekta, open source, ovo presovstvar projekta, kaj je vzlušati komputer in biloč. Prvno, in vzlušam. Vzlušam, da je projekta. Vzlušam, da je vzluša, kaj je vzluša, kaj je vzluša, Če ne bi se počunil, ne bomo vseč načo, tako, bomo pokazati, ki se vseč ne zelo. In, da se vseč ne zelo na komputer, da se je nekaj bljeni, da se vseč ne zelo načo. Zato, to je nekaj slajt, tabl, in zelo, bood. To je bilo. Corbood, 3Softwareproject. Corbood.org. To je, da je, na vseč ne zelo, Znamo, da je replazovana biose za 250 bolj. To je veliko vse. Vse možemo bolj svoj system v 500 ms. V 1.500 ms. je odgleda na vse, če je bilo vse. V tomrodi bilo nekaj prav. Fokus in deplojment do korobuča je vsega vsega vsega vsega. pizda je nekaj nekaj ne bo, da je srečnjet včas, da so prihledaj se, da se je všeč, nekaj ne bo, da jim je srečnjet včas. Znamenim tudi embaditosti, in tudi včas naprej klasteri, ker je to, da je projekta začala v v ljudi 1999. Prej ta je počak komputer, If you try to boot them, they will complain that there is no keyboard. So a guy must go around a thousand computers, plug the keyboard, press F1, go to another computer, and so on, and so on. So this was, let's say, the first where the project has been started. So here is Mr. PC. I think you should know it quite well, but maybe we can repeat some details. I'm not sure if I have mouse, so I can point. So this is the CPUs. Now we have a multiple of them. Each CPU has now each memory controller. Here is the DRM. This is the DIMS. You can replace on your board. Here is the North Bridge and South Bridge. And in between there is some kind of bus, which is FSB or hyper-transport bus. Or between North Bridge and South Bridge. There is also some buses. It doesn't matter which right now. And, of course, the South Bridge, which is having all your peripheral devices, like USB drives, serial port, and such stuff. And, of course, there is Flash, which has this program, either the BIOS or the core boot if you replace it already. What is quite interesting on this slide is that the red parts must be done by the core boot while the system is booting. So it's a lot of stuff to do, and we need to do it very quickly. So here is a little fairy tale about how to start a computer. So if you push the button, then at the beginning there is kind of power sequencing. So when the computer is starting, there are many, many voltage regulators, so you must wait until all voltages are at the right levels, and then the CPU gets started. And CPU will fetch the first instruction, which is this instruction, E9. And this is the damp of the flash chip. So if you take out the flash chip or the BIOS chip, let's say, out of the computer, so this is the last 16 bytes of it, and here is the first instruction. So if you decode this instruction, in fact it's a jump to another address, and because I'm not expecting that you can read the machine code by looking at it, so then you can go to the core boot and, oh look, here is the bootblock.elf, and you can run object dump on it and you can immediately see what's going on. So my presentation will be somehow intermixed with what is going on in the machine, and then where you can find it in the core boot code base, so you can follow the steps. At the beginning of our fairytale the computer starts in something which is called a real mode. This mode is 30 years old. It's like the first IBM PCs in 1980 were started in this mode, so the CPU is still compatible 30 years still because of this binary compatibility stuff and so on, so it really starts in this real mode, which is kind of derived from 8-bit computers, so we can address in one place only 64 bytes of RAM and totally one megabyte of RAM, which is not very nice because the core boot is written in C and we want to use GCC to compile the stuff and GCC on x86 is mostly producing the 32-bit code. So what we need to do is that we need to switch to protected mode in order to be able to execute a 32-bit code. How is it done is written here. It's basically only a few instructions. We need to load some descriptor table then we toggle some bits and that's it. So it was quite fast. OK, so in fact we have kind of very little assembly stuff in our project because most of it is written in C so this is kind of early beginning like in the Linux kernel and it starts, there is also kind of glue assembly so it set up the environment so it's kind of sane. But here is our first problem. So maybe we want to set up also the stack and you know when you start the computer you have no memory. So we need first somehow to cope with the fact that we want to run the C and we don't have any stack. Without the stack you cannot use the local variables you cannot use the read write global variables because you are executing code from ROM memory where you cannot write it there so you cannot do the instructions like push, pop, return you cannot do anything of this. So basically how we solve it there are two possibilities. One is to use special compiler called ROMCC this was written like ten years ago by Eric Wiedermann it's a C compiler written in one C file it's very ugly, very big, quite bloated but it has a very special thing it uses only CPU registers instead of the RAM so the local variables in C codes are just stored in the registers so of course it means you have only 128 bytes of available space but you need to live with that. Or the second possibility which is used on the modern CPUs is the cache SRAM it's a neat trick you can load the cache which will become valid with the garbage data from memory and you can use it because if you don't evict any cache lines then it is a RAM so it's like write back cache which never reaches a RAM so that's basically a trick how to do that so let's see, we are now in C and happy so first C code is executed in file which is called ROMStage.C this file is kind of main function which gets started in the C environment in this file there is an early initialization of the chipset and I will show you what's done there basically I think you already read that so we need to have access to the serial line because we want to read some debug messages and so on so we need to set up the serial line so it works and we can do print case to our screen of course we need to do the stuff to reach the serial line so we need to set up the LPC bus and hyper transport bus and so on in the meanwhile I am not expecting that you can see this because this hole is quite big but it's an invitation to read the code yourself basically here is the start is the cache SRAM you can see here we need the LPC bus we need the serial line and here we can print something on screen so we can have a look more until when I am done with this lecture then Daniel will speak about the flash ROM this will be about how to flash the flash chips on the motherboards and then you can come to our stand at AW building and we can have a look there we can talk more of course about this so in this environment we still run without any RAM so even if I put out all RAM from the board outside it will still boot and show those messages because we are using cache SRAM and at the end we just print no RAM so we don't continue anywhere in fact it would be possible to implement some game and so on 64 kilobytes is plenty of RAM so you are invited to do so if you feel you can do it so RAM in it, how does it work so first we need to get some data from the DIM modules to get this data there is another bus which is called I2C it is reachable from something bus controller and this was the green lines around the big scheme you need to program the chipset it means the north bridge or CPU if the memory controller is in the CPU you need to send some jadek commands to the RAM and basically you are done so it looks quite easy but it is not so in fact it is very complex task especially for DDR2 or DDR3 RAMs I use the slok count to just count only the code without any command lines so for the AMD in DDR it is like 2000 lines DDR2 4000 DDR3 8000 lines so it is non-trivial problem and for the DDR2 there is another problem called DQS timing you need to find a stroke signal which will assure that the right data is read from the memory and this timing is quite crucial and also it depends on the temperature so at the beginning you just need to find the right place where it starts to work and the place where it doesn't work again and then you take the half of it it is quite complex and complicated of course it is also depending on the PCB layout and temperature and such stuff so excuse me I am in 15 minutes for this so then the RAM stage is executed so in RAM stage we copied the core boot to the second stage we run from RAM in this stage we have to train the PCI express link and do all the resource enumeration on the PCI bus IO ports and of course prepare also some kind of tables which are required for the operating system and of course the ACPI and power management so basically a lot of stuff still needs to be done after the RAM is running here is some information about the tables so it is mostly IRQ routing tables that means that it is depending on the board layout you need to know which devices which IRQ line plus of course the ACPI which is very big specification and it contains as I have written here everything so it is very general a lot of stuff is hidden there of course we support it in the core boot and last thing is to load something it can be operating system it can be some game it can be very old legacy ROM like ROM basic which I have brought here so you can program something in very ancient language we use CBIOS this is a compatibility layer between core boot and operating system you know this from the QMU because when QMU loads you can see it so QMU is the layer in between which is used to load the operating system like legacy BIOS so that's it many thanks and please visit us at our booth I would be glad to see you there and I can explain more stuff in detail and tomorrow I will have some timing talk at the embedded froom and now the next one is Carol Daniel which will be speaking about how to flash the flash chips on the motherboard so again that's it thank you very much many thanks perfect timing