 So we're here at the Lenara Connect here in San Francisco, and who are you? I'm Palmer Debalt. I work on RISC-5 software. So I'm a maintainer of Binutils and GCC. I'm hoping to soon submit Linux patches as well as G-Lib C patches. So what is Sci-5? So Sci-5 is a company. So RISC-5, the ISA that I work on, was started as a research project by a group at the University of California, Berkeley. And it was started originally as an educational project. It turned out that there was enough interest in it, kind of outside of Berkeley, that it turned into a foundation supporting the ISA, the RISC-5 foundation. So it's now an open standard ISA. And Sci-5 is a company that was founded by the inventors of RISC-5 and sells chips and IP that are based on the RISC-5 instruction set. So were you before Sci-5, you were in the UC Berkeley? Yeah, so I was a grad student. Sure, yeah. Here. That's better? Yeah. So I was a grad student at UC Berkeley for four and a half or so years. I worked on RISC-5 stuff. I worked on, so I was in a computer architecture research group under Krzysztof Sanovic. I worked on some chips and I worked on a lot of software stuff while I was there. And then I kind of graduated and moved to Sci-5 to work full-time on software stuff. So RISC-5 is the fifth generation? Yeah, so RISC- Who those guys started all this RISC stuff at where and stuff? Yeah, so RISC originally started back in the 1980s as a course project with Dave Patterson who eventually became a professor at UC Berkeley. And it went on to start kind of Mips and Spark were competing RISC architectures based out of Berkeley and Stanford and those were both commercialized. The RISC project stayed largely educational up until RISC-5, which again was started as an educational ISA, but has turned into a kind of industrial strength ISA. And ARM made an advanced RISC machine. It was inspired by those papers in the 80s in the beginning? Yeah, so I'm not really an ISA history guy, but my understanding is that ARM was another one of these machines and that kind of wave of innovation that started after the original RISC idea. So nobody really kind of copied the ISA exactly, but there were a lot of fundamental ideas in RISC, which was basically designing your processor around things that compilers can generate code for and looking for total performance of the machine instead of kind of cleanliness or orthogonality of the ISA design and that sort of stuff. So is the idea that it's an architecture or a design that's kind of for university education? Well, it was started because there was no viable alternative for an ISA if you wanted to do computer architectural research in an educational setting. So basically, you know, you couldn't use MIPS or OpenRisk because they're not very good anymore. You know, MIPS was kind of old. Alpha was used for a while, but it's fallen out of favor because it's also old. ARM and X86 are both just intractable to implement as a university program. If you wanted to do kind of computer architecture research, build chips and that sort of stuff. So there were no viable options. So instead, the founders started working on RISC 5, which is a new ISA designed to be simple to implement, have a core that's usable for, you know, even undergraduate education and that sort of stuff, but be big enough to run a full copy of Linux and have floating point and all that good stuff. So it's a simple architecture? It was designed to be as simple as possible. It went back to sort of the RISC philosophy, which is only add the things that you need and have a good reason for adding things that you're adding. But couldn't you have done one of the Cortex M0 or something like that? That's not enough. It doesn't run a full Linux. Well, it doesn't run Linux. It's still based on ARM, so there's a lot of ISA complexity and there's some pain involved in dealing with the proprietary ISA. So that's a, is it a free and open? RISC 5, the ISA, is a free and open standard. It's governed by a standard organization, which has 50-some members, including some kind of big companies. And the, we have something called Rocket Chip, which is an open-source implementation of the RISC 5 ISA. And all of SyFive's products are based on Rocket Chip, though with a little bit of extra kind of special sauce added in that we sell and obviously kind of support and testing and all that good stuff. Do you have companies interested? Yeah, I mean there's a handful of companies today selling RISC 5 IP and systems. I know we have Andes, which is a Chinese microcontroller manufacturer, which is the NDS32 architecture. They have some guys working on the RISC 5 software stuff. And the MicroSemi, who is an FPGA manufacturer, has a soft core based on RISC 5 that's been licensed from SyFive that they have as part of their development environment. There's a handful of educational projects as well. And I think there are a couple of commercial, like one-off implementations of RISC 5 in embedded land. But I think there's nothing commercial that runs kind of Linux right now. And you have some code you want to submit, like you were working on the Wi-Fi? Well, I was, so basically we're hoping to submit Linux patches kind of soon. We've gotten some amount of approval for them and we're hoping to get into Linux next. We're hoping to kind of do it today, maybe, depending on how many people I run into talk to here. We'll do it sometime this week. Because there's lots of maintainers around here. Yeah, so this is why I showed up. Basically, I'm kind of new to the open source community. And when I found out that this was going on, we thought, hey, be a great opportunity to just come by and meet some people and say hi and that sort of stuff. So I ran into a couple of people I knew and chatted with them for a little bit and hopefully we'll meet some more people. So you have an office right here nearby? Yeah, the office is maybe like five miles away. It's at the corner of 92 and 101. And how many people there? I don't know. That's a good question. It's definitely way more than 10, but it's also less than 100. It's probably like 30, 40, something like that. And what do they do, all these people? Engineers? Yeah, a vast majority of them are engineers. It's a largely engineering-focused company because it's a startup so it's pretty early. So everybody's in the sci-fi and as a startup. Since when? So the company started, I think a year or so ago? I've been there since March. The company must have started maybe closer to two years ago. Yeah. All right. And you have lots of work to do? Yeah. Are you the main code guy? So I am a maintainer of Binutils, GCC, and then hopefully Linux when we get our patches upstream and G-Lib C. We also have co-maintenors on all of those, some of whom work at sci-fi and some of whom are other RISC-5 member associations. We are GCC maintainers from Andes, who I mentioned is Keto Chang. And Andrew Waterman, who's also at sci-fi, helps me maintain Binutils and GCC. And then Andrew U... Sorry, Albert U, too many names, will be the Linux co-maintenor. Have you worked on any ARM stuff before? I actually kind of missed the whole ARM bandwagon, if you will, because I ended up at a company called Tylera a few years ago, and that's where I worked. So I worked on the Tile ISAs, not really any ARM stuff. But then they started doing a whole bunch of multi-core ARM solutions. You were not part of that? I was in grad school by then. And to the best of my knowledge, they eventually got bought, and I think they are working on ARM systems now. But that's kind of... It's been a long time. All right. Cool. So, there it is. What's going to happen in the next year at your company? Well, the big thing on our side is to get Linux and G-Lipsy upstream so we can start getting into distros. We've announced that we're releasing a development board based on one of our chips, hopefully in the first quarter of 2018, which will be a Linux-capable sci-fi chip in the first five years. Make by who? TSMC. TSMC? Yeah. So, yeah, that will be like a quad-core chip. Runs Linux, has caches, and has memory and all that good stuff. And is a sci-fi chip? It is a sci-fi chip, yeah. And does any talk about how many cores are performing? Yeah, so it'll be a four-core chip, which I think we released all this during Hot Chips. Yeah, it'll be a four-core chip, and it's reasonably fast. So Rocket is a five-stage in-order pipeline that's kind of a pretty beefy one. So it will perform like that. We don't have exact performance numbers yet because we don't have the chip. Right. And lots of activity here in the Silicon Valley, you also have like a meet-up or something in the next few days, right? Yeah, yeah, we're just... So when we found out that there were a bunch of people in town for Lunar Connect, we thought we might have a few people over for a beer. It's been posted on Twitter and the website. It's on Wednesday night. So I'm running around talking to people, and if anyone wants to come, I believe it's all online. You can probably dig it up out.