 Welcome, today's lecture is, it is a brief overview of some basic VLSI physical design automation concepts. I missed the, missed in the title the, it is physical design automation that we are going to deal with, not general VLSI design, which also includes logical design automation. So, in this and next couple of lectures, there will be some basic fundamental simplistic overview, overview of some fundamental concepts will be given without too much rigor and very formal treatment. So, what VLSI physical design automation is the stage in the, design automation after the logical design automation. In the logical design automation, the tools, automation tools convert a behavioral specification given in some high level language or some hardware description language is that is converted into a logic circuit in terms of gates or maybe in terms of NMOS, PMOS switches. And this, so this automated process is followed with the process of physical design, the flow of physical design, which a logic net list is converted into a layout. So, basically this is logic to layout automation. So, in this and the next couple of lectures, I will focus on some, you know, I will give you a brief overview of some simple fundamental basic concepts of layout automation. I mean, it is a subject by itself. So, you can I mean, you know, look up the course material of a course on VLSI CAD and that will give you more details of this. So, in the physical design automation cycle, one like, you know, there are several stages, the ones which we are going to concentrate, I am going to concentrate on rather overview in this few lecture, two-three lectures at this first three stages, which where things begin with circuit partitioning, a very general kind of stage, a very important stage to manage the complexity of large designs. Circuit partitioning is followed by floor planning and placement. With the help of partitioning of a circuit, a chip area is floor planned and different zones of the chip area are allowed sort of assigned to earmark for different sub designs. Typically, this could be like, you know, this could be manual design into a very logical subsystems of the original big complex design. So, floor planning is kind of think, one can think of it as approximate like, you know, getting an approximate idea of how the layout would look like, which sub designs would be on, in which part portion of the chip, how much area in which part of the chip would be reserved for, which sub design, that is the general objective of floor plan. It is a bit course level process. At the final level, the placement process shown here, placement process will find out computer details, detailed locations of the cells. The cells in the blocks or the cells in the sub designs are to be placed in appropriate locations of the portion of the area earmarked for that sub design. So, that is the placement. So, at the end of placement, we have the, we have this regions where the cells are going to be placed, in the orientation. So, we also know more or less precisely the location of the pins, connection pins of those cells, which have been placed. And this information, where the connection pins are at which coordinates of the chip, this information is fed to the routing stage. The routing stage, the routing stage will make use of this placement information and connect up this, like you know, layout to net signal nets or wires based on the locations of their connection, the terminal pins. So, that is the router's job. Our overview will stop more or less over here with some, also included will be some, like you know, overview of the core concepts of static timing analysis and how they interact with, how they influence this physical design process flow. So, that will be subject of the next couple of lectures. So, in this lecture, I will just skim through some basic concepts and for routing, I will give illustrate couple of algorithms, again basic algorithms to some example. So, I missed out something. I have deliberately kept this blank. There is, one can look at different levels of details. After routing, there will be, within the routing, there will be some specific routing for clock tree as well as power grid, power and ground network. And after routing stage, there will be typically stage of compaction of the layout, will be a stage of verification of the layout and so on, so forth, extraction, a circuit simulation again, post layout simulation. So, let us, let me begin with circuit partitioning, a few remarks on that. So, circuit partitioning is about conquering the complexity of implementation of a large design by partitioning the large circuit into subcircuits. Basically, the automation is required for very large designs, complex digital systems where, like you know, fairly complicated behavior requires a lot of, like you know, is, is realized with the help of tens of thousands of millions of gates. So, the design is extremely complex, large scale. So, the algorithms, even if they are efficient in terms of run time, the size of the problem is so big that to really aim for efficient implementation, efficient run time, one has to, like you know, use divide and conquer approach, wherein we will divide the problem, solve the sub problems more or less independently, then conquer, then kind of stitch together solutions of the sub problems and get, obtain a good, apparently good solution of the big problem. This technique does not necessarily always work perfectly, but like you know, it is a obvious natural paradigm for breaking down the complexity of problem by using this divide and conquer approach. So, we will partition the large design into subcircuits and these subcircuits I will call blocks of the partition. So, each block is a subcircuit and while partitioning the factors such as sizes of the block, how big the block is allowed to be, how many gates does it, is it allowed to have this kind of factor as well as the important factor of number of interconnections between the blocks, these factors are extremely important while deciding the partition. So, we would like to say, keep the sizes of the blocks under control, they should not be too small or too large, too small would be a waste of like you know, the resource that block is going to be laid out on, layout of the block is going to be made up and then connections also we would like them to be minimized for some fairly intuitive reasons as would be clear in the course of this lecture, next lectures. So, partitioning is a very interesting large scale optimization problem, very well researched and has applications in not just VLSI CAD, but a large set of applications in some scientific computing and various other domains. So, here is a small kind of toy illustration of circuit partitioning concept. So, here is on the left, we have a circuit with this 8 gates A 2 A B C D E F G H and here, there are two dotted lines dashed lines marked here, one is label cut line which is basic, which is separating gates A B C and D from the rest that is E F G H. So, cut one is separating the block of the circuit A B C D from the other block E F G H, whereas the this vertical cut line, I mean this particular dotted cut line which I labeled cut 2 is separating the block containing A B D and E these gates from the block containing the gates C F G H. So, these are these two cuts are like describing two different partitions, each partition having two blocks, but the quality of this partition is or the this different partitions will have different like you know implication as far as this layout is concerned and that is one of the most obvious thing that you see over here is that for the first partition which we have obtained using cut one, which separates A B C D from E F G H, you see that there are only two connections going from one side of the going from one block to the other block that is the layout of one of the blocks between the layout of the these two blocks there are only two connections crossing. So, it indicates at number like long running wires will be relatively few. On the other hand for the other cut which separates A B D E from C F G H, you see that there are as many as four signal nets being cut between this blocks in between the layout of this layouts of this blocks. So, that means there is a more there is more chance of very long running wires and that clearly like from the intuitively from the timing point of view it could be a bad layout. By the way this example and this figures are taken from the book V R S F physical design title is V R S F physical design from graph partitioning to timing closure the authors are Cahang, Lienig, Markhow and Hu is published by Springer. It is a good compact book with several topics of physical design explained very well. Algorithms details are given where is plus lot of illustrations are there and a good book for both students as well as practitioners. So, this as well as many other few other examples will be borrowed from this book. So, some concepts in partitioning the notion of the terminology partition or block is a group collection of components or cells. In general very typically one looks for two way partitioning partition into two block, but one can in general talk about k way partitioning where the task is to divide a circuit into k partitions. So, very often are like very typically partitioning problem is studied in like with abstract graph models where the nodes represent the cells and edges represent the connection between the cells. Sometimes like you know in the context of V L S I had the extension of graph that is hyper graph concept is more often used. So, here is a net list and that net list the cells of that net list A, B, C, D whatever up to G are represented by the nodes of this graph. The way the cells are connected to each other in some sense may be sometimes with the direction information sometimes without direction information here in this case there is no direction information captured here. So, not everything that we know about a circuit is required for the sake of partitioning like only the abstract essence is required and that is captured in the graph model and that graph is subject to partitioning algorithms of like various complexity or cleverness degrees of cleverness and we get useful solutions or information out of it. More generally it is so called hyper graph model is used which I am not going to go into, but very popular standard model you look up this literature more and you will find I mean you will encounter it very easily and like there will be very lucid descriptions or explanations of that concept and so yeah I think these are that was just very like you know just few terminology few terms that one encounters in the context of partitioning. There will be I will give once special lecture on which partitioning alone which will give us illustration of one of the central like you know pioneering algorithm heuristic for circuit partitioning. Of course, it will there will not be something it will not be very clever kind of algorithm which with lot of sophistication, but it turned out to be some an algorithm which like you know we solved a problem decently and which gave rise to lot of very interesting variations and extensions. So, that is later so partitioning I will I will skip over to the next this in fact after partitioning as I said partitioning would have been used for floor plan deciding the floor plan of the of the chip like if some good partition is known which is like you know which divides the big circuit into some very like modular logical sub circuits or some algorithm finds is good partitions good blocks then correspondingly the chip area is divided into reasonably appropriately large or appropriately shaped rectangles or like you know regions and different regions are earmarked for different sub designs which have been obtained in the process of partitioning. After floor planning one gets rough idea over where each sub design is going to be laid where the layout of each one of the sub designs is going to be and then the placement problem is going to detail out the exact locations of the cells which is within each block of circuit and within the corresponding area of the chip. So, placement here placement is the problem where we are given a net list and like logic net list over the circuit we have to find the exact locations of the cells. The objectives are like the primary objectives are area and wire length. We like to for natural reasons, intuitive reasons we would like to minimize the area of the layout because one typically wants as small as possible VLSH chips and we would also like to minimize the wire length either the total wire length or the maximum length of any particular wire. So, all kind of combination of such objectives will be used for optimization. Wire length is directly related to complexity of routing as well as the delay the timing performance critic. So, placement is in complex problem because it is going to deal with a large problem and it has to it has both combinatorial and combinatorial as well as geometric character and lot of research has happened in this area and there is a variety of approaches fairly interesting subject by itself. So, let us just another in one extra once specific lecture I would take I will illustrate once interesting example of a placement algorithm just for the sake of flavor. So, that will be later. So, I will just give a very brief introduction to the notions involved in placement or some example not algorithm itself in this lecture in the later lecture there will be illustration of a specific algorithm which I will just mention which one. So, placement as shown again in this figure in this figure from the same book that I mentioned earlier there is this there is a net list with this eight gates and if the target of the placement is a one dimensional like one dimensional chip where in we have lot of we can accommodate a row of standard cells for example, then the placement problem is really about like ordering the cells each one of the cells which would fit on a it would be implemented as a standard cell linear the placement is essentially finding deciding on a linear ordering sequential ordering of this cells depending on which order we lay in which order we lay out this cells the length of the wires would be optimized a total length of the maximum length of any wire would be optimized and that would give rise to like you know different degrees of timing performance. If the target chip is two dimensional then the layout might look like this like not layout of placement rather placement might look like this in two different rows or like you know whatever it in 2D fashion and depending on the placement of cells in different positions the the routing the wires might look congested or might become bit long or total wire length might be large and the router might have more difficulty and the timing might might be better or worse depending on the quality of the placement. After placement and routing one would typically have a picture like this where we have this this gates placed in the standard say as standard cells like in two different rows with some sometimes some gas between them through which routing can be done, but there will be optimization of this placement done by the placement algorithm and a router will take care of finding the best possible route. So, that the number of the amount of routing region is as minimum as possible so that the whole area is as small as possible at the same time the locations of the terminals IO pads will also be taken into account while doing this routing or placement placement and routing. So, in the end we would have a layout of this kind and most like for large designs it will have to be necessarily automated. Here is a picture of how placement can like influence the quality of routing. So, both these pictures figures show some different placements of a set of cells from a to whatever g or a to k what is a, b, c, d, f, j, k. They roughly this both this placement roughly occupy the same area and so that means the same amount of routing area, but depending, but the placement on the left and left hand side is clearly like you know something that favors a better routing. So, as seen like although this is not really routing, but we know that if the wires are going to go from this terminals of this cells to this terminals and so on so forth. This information is known because the placement process has computed that the locations of the pins and the circuit information has the connections connect how the pins are connected to each other. So, that gives us some picture of approximate picture of how the routing will look like whereas in this the routing appears to be much worse. So, like you know so the placement influences the quality of routing in a significant fashion. So, placement is a very important part of the process. The placement algorithms there is a rich set of placement algorithms broadly classified into this paradigms. First one is top down not in specific order of like but first popular paradigm is top down which is a recursive paradigm. Then this iterative method for placement like you know VLSI layout place circuit placement. Then this construct your incremental process of generating a layout or placement and they are quite interesting mathematical approaches based on linear algebra matrix computations or mathematical programming of course in particular say quadratic programming. Many of them use Eigen spectrums Eigen values and Eigen vectors of matrix called Laplacian which is a matrix obtained by the connectivity from the connectivity information. This top down approach is a recursive approach which typically uses two way or min cut partitioning which partition the circuit into two parts and two these two different parts are to be laid out on two like you know roughly equal portions of the chip and these two portions of the chip would have been found by like choosing a horizontal or vertical cut line of dividing the chip area into two parts. So, the circuit is partitioned into two blocks and the chip is partitioned into two parts and then we have two separate sub problems which have which can which should be solved separately and then maybe with some awareness of each other and then this solution should be stitched together. If each one of the sub problems itself is not small enough then we have to do this we can go ahead and do the same process recursively partition each one of the blocks into two parts, but now like you know use the alternative like other kind of cut line if we had earlier chosen to divide the chip into two parts left and right now for the next level we can divide the chip into each portion of the chip left right portion into top and bottom left top and left bottom similarly right top and right bottom. So, we can have alternating like you know division or space division of the chip and correspondingly we will be recursively subdividing the given net list also. So, appropriate circuit partitioning algorithm would be used depending on the efficiency or quality. In fact, many different heuristics can be tried one does not always put faith in full faith in just one algorithm I mean most of these problems are hard NP hard and so very little of guarantees are given about the qualities, but roughly the benchmarking has would indicate that many of these algorithms are good from quite well still one would like to try out different algorithms and choose the best result of one of the I mean among them. Then the about iterative paradigm, iterative algorithms one of the most well known algorithm is like based on the even more celebrated well known like paradigm called simulated handling which is like an extension of metropolis algorithm regarded as one of the top 10 algorithms of the century. Very popular paradigm like which is based on interesting theory of Markov pros chains and so it does it is not extremely fast, but it does tend to give like you know good solutions if we run it long enough and it is always available as one of the options in the kit of for the placement algorithms. Similar to another important iterative method that is again based on some interesting concept of from physics is the so called force directed placement. The force directed placement is based on like you know is it uses this mass spring model and you know so the cells which are like regarded as masses and connections between the cells were depending on the degree of connection, the amount of connection a spring is strong or a weak spring it attached and based on the forces exerted this cells the masses will kind of settle down in some position. And that position is used as a as an estimate or as an approximation to the placement detail the locations. Constructive algorithms are incremental they start with some cells in the center and then place highly connected adjacent models around them. So, it is incremental used to have you make some clever decision about what to place first which seems to be at the center of the things and then based on that those location and the connectivity of some of the modules which are highly connected to this set of already placed cells we start placing the those at those highly connected adjacent modules around them and so on so forth. Then we will have less connected less thickly connected modules will be in the outers like zone and so on. So, this incremental thing might look nice, but again the choice of which cells to choose which how to estimate how to be efficiently compute good neighborhood or good cells for the next like placement and all that there is lot of cleverness possible here lot various algorithms have been would have been heuristics would have been have been designed for this paradigm. As I have already mentioned about linear algebraic approaches they use the Eigen spectrum of Laplacian. So, and to kind of embed the prop convert the convenient more or less combinatorial problem of finding the locations relative look or the positions at which the cells should be placed. This problem is converted into a geometric problem where the geometric information is obtained with the help of several Eigen vectors for example, and Eigen vectors which Eigen vectors that would depend on the say smallest Eigen values or smallest set of smallest certain smallest number of smallest Eigen values. So, it is backed by interesting theory from like linear algebra and spectral graphs. One of the main theorems is easy, but important theorems which is whose variations are used here is the so called Hall's theorem. So, similar to very similar to this linear algebraic Eigen value Eigen vector based approaches there is a mathematical programming approach based on quadratic programming where we use some of the squares of like the kind of Euclidean distance square of the Euclidean length of the nets. So, there will be some it will have some of the squares kind of form. So, it will have the quadratic objective function and using again Lagrangian techniques or calculus non-linear programming ideas one can arrive at good solutions with this interesting approaches. And of course, with some post processing one and with combining this solutions with some other heuristics one can get like you know better solutions. So, this so this techniques will not claim to be the best techniques by themselves they can be variously combined with each other and or like independently used for finding the best and so on. So, there is a fairly broad set of algorithms of placement. So, in one lecture I am going to focus on the placement by partitioning slightly informal introduction or illustration would be given and that placement by partitioning is the top down approach where a partitioning may be targeted for 1 D or 2 D layout of a chip and the net list will be partitioned into two parts at each level of the recursion. The with the objective that they should be placed into two parts which we have a cut the chip into may be left and right part or top and bottom part. The aim would be to minimize the number of crossing wires and if the sub problems still happen to be complex in sense of size then we recursively continue the same process, but the chip area sub areas will be partitioned with alternating directions horizontal vertical and so on and so forth. So, that is a rough idea about placement by partitioning after this I will move to the routing like some disk like overview of routing algorithms. Here I will have couple of concrete illustrations, but very informal very sketchy just highlighting the main ideas which are very intuitive like other than. So, at the end of this lecture I would have given you couple of examples of routing then in this couple of subsequent lectures there will be an illustration of placement algorithm specifically placement by partitioning with the idea of terminal propagation separate lecture on will be there on partitioning also a simple well known algorithm called Koerning-Hanlin will be discussed there and in another lecture I would give you some idea of overview of the main core concepts of timing analysis. Again the graph model how the graph model is used and how like this timing I mean using the delay information the so called arrival times actual arrival times and required arrival times are computed that will be in a separate lecture and how the by timing is important from the perspective physical design flow that also will be remarked. So, next I will be going to routing so after having taken a very very brief look at the concepts of partitioning and placement I will just give a couple of examples of concepts involved in the routing the algorithmic ideas involved in the routing. Routing as a remarked before is about like you know finding the layout for the actual the wires the actual layout for these signal nets because at the end of partitioning we know the locations of the terminal pins of every terminal pins of every signal net some of them are coming from the periphery of the boundary of the chip some are coming from obviously driven by the cells. So, with this information we have fairly complex task of like routing possibly millions of wires. So, it is a very large scale problem again so again in some sense like of course, we can look at sub portions and do routing separately, but routing itself is divided into two phases there is something called global routing which is a bit course level routing and there is something called detailed routing. So, these are the major phases in routing the global routing would have the task of assigning nets the signal nets to routing areas the after placement we have the idea we have know exactly where the cells are and we know which areas of the chip are free for routing the wires routing the signal nets. So, this routable areas are divided into sub areas called routing regions and so there is a vast collection of routing regions maybe they are like you know rectangles or square like shapes regions and the global routing is to like global routing would identify for every net which of this sub area which of this routing regions the signal net should be laid out in sort of know and the detailed routing is going to actually like you know find out the particular track inside each region along which the wire will be wires layout will be fixed. So, global routing is kind of going to look at big problem the whole chip the whole set of routing regions and all signal nets and for every net it is going to find this set of routing regions through which a net will ideally pass. So, that the effect I mean like the routes are as short as possible hopefully detailed routing is going to look at each sub region and within the sub region it is going to fix the position of the grid wire the track on which the wire will be on which layer on which horizontal track on which vertical kind of branch all that will be decided by detailed routing. So, global routing after placement we have the exact terminal locations and we want to assign this this routing regions so called which could be either channels or switch boxes you want to find which of this channels and switch boxes should be used to root the net a particular net and this has to be done for each net detailed routing will determine the exact root and layers for each net within the assigned routing region that is what I just remarked. So, here is one illustration from the book of Sherwani. So, these are this blue port rectangles are the regions where the cells have been placed and this dotted red lines are like the approximate picture of how the wires will be rooted and then the detailed routing is going to fix exact location the horizontal vertical tracks vertical branches along which this wire should go this is still just abstract picture, but this is one way of like you know visualizing what global routing and detailed routing different mean. Here is another picture of example from taken from the net like by a professor she is from the course of Texas M. in university. So, here is the set of cells and some wires connecting them then the remaining the regions outside these cell cell placed cells is the root able region and that region is broken up into rectangle shapes and which are called channels. So, for example, this is one channel this is another channel one more channel here. So, so many channels and a few switch boxes like this these are called switch boxes. So, this regions are identified by the by a pre processing part of global routing and then for every net every one of this connect signal net the global router would identify that this particular net which goes from D to this particular pin of B should go through this channel and then should go through this switch box and through this particular channel and on to this particular pin and so on so forth. So, for every net such like you know a sequence of the channels and switch boxes would be identified then the detailed routing is going to look at each channel and each switch box and fix the positions of the wires tracks which track and which branch vertical branch which horizontal track that will be fixed by the detailed routing that will be could be something like this. Then to model the algorithms to kind of describe the algorithms a routing regions are represented typically using a graph graph model again graph graph is a very popular data structure in this combinatorial algorithms for physical design automation. The nodes of the graph would represent the routing sub regions like channels and switch boxes and edges represent the ideal adjacencies for each connection each net the router determines a path with within the graph that connects the terminal pins or maybe like something a tree not just a path as I will illustrate in the next example. But the important thing is that the path can travel can only travels those nodes and edges of that graph which have sufficient remaining routing resources for example, this is a sequential process one net at a time is routed maybe in the worst case just one net at a time and then after laying out after figuring out approximate routes for each one of this nets done so far we would have we should reduce the capacities of those regions because some of them have been committed for like for for the layout of some of the segments of the nets. So, the resource availability of each routing region or each channel is going to be updated while like you know and use that that information would be used while figuring out the global route for the next net that is to be considered that would be considered. So, this graph models have the nodes and edges like with capturing the appropriate information about the routing regions and their adjacency, but the capacities in some kind of resource capacity information is also available which will which will be incrementally updated decrement rather to keep track of how much is the available routing resource within that region. One of the specific kinds of graph used in this route global routing is so called grid graph which so this grid graph is a commonly used data structure or graph structure in this like the example is over here this example is from Kang's book. So, whole chip area is divided into into this grid the size of the grid will be will be chosen appropriately. If you want if you want to use this idea for global routing essentially for course approximate routing then this grid can be course. If you want this idea of grid graph to be used for detailed routing like you know we want to get more accurate idea then the grid should be very much finer along the grid we will have like you know there will be places where this cells are placed and based on that part of this grid cells will be like you know we would have reduced capacity for routing purpose and so on. So, for example, the cell number 12 has plenty of capacity routing capacity cell number 11 grids this is not cell of the circuit, but cell of the grid this cell grid cell of the chip will have more routing capacity whereas, something like cell number grid cell number 13 will have very little area for routing and so on. And the adjacency of this grid cells is captured by edges the grid cells are represented by nodes of this graph and some shortest path or variations of shortest path algorithms are going to be implemented on such graph structures which will lead to the solutions of global routing problems. Similar to grid graph rather not similar alternate as an alternative to grid graph there is something called channel adjacency graph where every channel say channel 1, 2, 3, 4 all each one of the channel is represented by a node of a graph and depending on which channels are adjacent there is an edge between the nodes of the corresponding channels. So, channel 1 and channel 2 are adjacent so there is an edge again the this there will be some could be some capacity information of this nodes and edges reflecting the routing capacities or some other factors. So, but for the sake of illustration I am going to like it lead you through once very simple paradigm called maze routing in various like other context you might have noticed heard about maze routing it is very popular it is one of the earliest algorithms for the routing problem. So, as shown over here like you know maze routing will use some kind of grid and the this dark blue portions not dark sorry this light blue portions are say represent things some obstacles in the maze which in the maze and these are indeed the places where cell the logic circuit cells have been placed. So, these are not available for routing whereas, this empty like you know wide background grid cells are available for routing supposing a net has to connection has to be made from somewhere over here to some place over here then correspondingly like we will have to find some kind of shortest path through this grid the maze and that would evidently be this if you just look at the other alternative which will be bit longer than this. So, there are more possibilities than this, but one such good short like short as possible often the shortest possible sequence of such grid cells is used for the purpose of like you know eventual routing of a signal wire from s to t and once that wire from s to once that is chosen then these capacities of each one of the grid cells along this path would be decremented to reflect that like some part partial use of that those routing regions. Now, I will take you through an illustration of a simple idea. So, supposing here is like you know a chip area which is divided into this grid and this dark blue portions are the are the regions where you cannot do any routing because this is where this circuit cells have been placed and let us say there are some in this grid cells marked a, b, c, d we have some pins which need to be connected by a single net may be that net is getting driven by a and is driving some pin of a because gate in this zone c or in zone b as well as in zone d these are the grid cell zones. So, we would like hope you would like to eventually arrive at some you know so called a net of this kind a driving it signal flowing to b as well as to c as well as to d. So, how is this to be computed? So, this is the initial data for every net which is multi term which could be a multi terminal net you would have such for like a routing cells marked as the thing terminals to be connected terminal cells or grid cells to be connected. So, main idea in this algorithm is so called a wave front and very natural idea. So, what we are going to do is propagate wave waves and like when the and you know in synchronous fashion. So, from every cell you will start up start out of wave which will like you know move one distance one neighboring cell further and when this wave fronts meet each other that is the time we know that a short connection is like you know found out and like you know bit of book keeping is required with the with the help of so called the front of the wave wave front and that will give us the final answers help in get help us in getting the layout of a net connecting a b c d. So, we start a wave front in the first like step the wave front would be at the distance one from the sources. So, this is cell routing cell marked grid cell marked one a one a indicating that it is a distance one from a it is part of the wave front that is started from a. Similarly, from b the wave front reaches this cell as well as this and this from c it reaches here it is marked one c and one c and from d it reaches this two in the next step. So, note that the wave fronts are not still like you know touch each other whereas, in the next step from one c the and this cells the wave front will start will reach this this this as well as this, but before growing the wave wave front of c we would have grown the wave front of b and b is wave front would have reached over here. So, this would have been marked to b. So, this in the next step b is wave front would have reached here marked in yellow to b a is wave front would have reached this locations this cells marked to a to a to a b is wave front would have reached here here as well as here. Now, when you start like you know updating the wave front of c you notice that this becomes the new cell grid cell on the wave front this also is on wave front of c, but while like growing the wave front from here to here one notices that we are already adjacent to the wave front touching the wave front of b and that indicates that now we have identified like a kind of a sequence of grid cells through which a short connection can be made between c and b and that we like you know fix in this. Similarly, the wave front of b has been expanded extended to cover visit 2 d and this particular cell. So, only this connection has been made whereas, in the next next step this wave front of a is going to reach such cells this this one where and this one wave front of b will reach here wave front of c will reach here here here and over here also and when we start going wave front of d will notice that wave front of c which has reached here is clashing is touching the wave front of d. So, d and c would get connected in the next clock cycle in the next step as shown over here the wave front of c would have reached here and when we start growing the wave front of d we realize that this is adjust already adjacent to the wave wave front of c and that means a connection between d and c has been good connection has been found out. That means a good set of sequence of grid cells would have been identified for the purpose of detail routing which is to be done later. Now still we have so far managed to connect b a and b c and d a is still remaining but now looking at a wave front we realize that in the very next step it is going to become evident that like you know when you try to grow the wave front of a from 3 a to this it would realize that it is already touching the wave front of b. So, connection between a and b would also be found out in the next step and that would be this. So, this will complete d like you know an approximately good there this problem of finding so such so called steiner tree is connecting a set of terminals is again an NP hard problem even in the rectilinear Manhattan kind of setup. So, one does not expect optimal answers for large problems. So, this is can this can be regarded as one clever heuristic which is very easy to implement on obvious data structures and also fairly paralysable has some benefits in terms of elegance and simplicity. So, such a heuristic is going to give you some decent quality multi terminals steiner tree net layout of a net and variations of this ideas. In fact, what has shown here is not the basic idea that was due to Lee and Moore called a maze routing idea which was essentially for two terminal like nets very simplified assumption was made that every net is just having two terminals a source and a target source and a sink and then some this wave front wave propagation idea was used to like identify the shortest path through this grid graph through this grid cell from source to the target and then like some extensions of this idea were made for multi terminal nets. And so this just to indicate that various similar ideas are possible I have given you like outline of one idea that is possible this I am not giving any pseudo code for that it would be an interesting exercise to try to capture it as a well defined heuristic and how the book keeping is precisely done and when exactly the labels are updated when exactly the wave front like you know when does one realize that wave fronts are touching and it is a time to kind of capture that information and record it as a good connection all that went to stop and so on all that would be like an interesting exercise to figure out like and convert this into pseudo code and then into a regular implementation and maybe parallelization other than this so this was an this can be regarded as a typical example of a simple example of global routing like identifying the regions the grid cell regions through which a multi terminal network net should be laid out and then at a detailed routing one would have several such problems where we have several different channels and for each channel we know where the net enters through a pin and like channels are those regions where the pins are on either side the longer sides opposite sides and like you know we have specific specification of which pins are to be connected to which pin is to be connected to which one it could be multi terminal pin or it could be two terminal pins and within a channel we have some number of horizontal tracks and we have to figure out exact horizontal track that should be used for the layout and corresponding vertical connections from the pins to that track and one of the natural optimization criterion would be to use minimum number of tracks. So, that in the time of compaction of the layout this channel can be reduced in size in the beginning with some pessimism we would have allowed a big enough channel with large number with sufficient many like you know tracks and if we optimize well the number of tracks used would be as few as possible would help us like you know string this channel into a narrower channel at the time of compaction and which would which would improve the size or the area requirement of that particular layout. So, here is an example where we have a channel with this pins marked 1 2 3 4 and so on some of the pins are not marked indicating that those pins are not to be used there is no net like being connected to this pins you see that sometimes net is connecting pins on the same side 1 and 1 there is no pin number 1 on the other side sometimes net connects something like say 5 pin number 5 to pin number 5 on the other side. So, as well as there is another pin number 5. So, this is the multi terminal net connecting this pin with this two pins number 5. So, you can have different kinds of nets and a solution would look like this which would make use of horizontal tracks like this which are the main trunks of this net layouts and vertical so called branches and so on. So, this net has this particular trunk which is on this horizontal track and connected using this vertical branch and this vertical branch. So, there will be a layer of horizontal wires tracks and there will be may be 1 or 2 layers of vertical branches why more that would become clear because sometimes the nets can have overlapping positions and the vertical branches might overlap. So, you to have like you know to have them separately laid out you might require more than one vertical layer. So, channel routing is also very well investigated problem and one of the very basic idea like for starters is the so called left edge algorithm. So, this is a very simple very greedy algorithm which is like I mean which is where one begins the study of such algorithms because it is based on like you know simple greedy algorithm and I mean strategy which it shows which is which can be shown to be optimal in case of in the absence of certain constraints in case of very simple highly simplified assumptions. For example, if you assume that all the nets are just 2 terminal nets. So, 1 net 1 is connecting this pin with this and nothing else net 2 is connecting this pin with this 1. So, all that all the nets here are just 2 terminal nets and we also assume that we have say plenty of vertical layers plenty means 2 or 3 whatever that should suffice. So, it just a matter of then like because we have we do not have any restriction number of vertical layers for routing the for fixing the vertical branches. The problem really boils down to like assigning the horizontal like you know the strungs to appropriate tracks. So, net number 6 should have the scope from this left end point to that this right end point because this is the pin left most pin of net number 6 and this is the right most pin of net number 6. So, nets 6 has to be laid out in this zone may be on this track or some other track. Net number 1 will start at this x coordinate and will go up to this it need not be on this track this track may not be the best choice for net number 1 and so on. So, what this algorithm does is source this the nets by the left end point. So, here net number 6 will be the first to be considered because it is left end point is the earliest the net number 3 or 1 will be considered next because there left end point is the next earliest and so on. So, now, we look at them 1 by 1 so net number 6. So, that is the first one in the sorted list because it is it starts at the earliest left most end point. So, this is rooted laid out on the first available track horizontal track and obviously, connection is made with the help of 1 vertical metal layer wire here and 1 of the vertical wires available from here to here wire will be placed over here connecting the vertical segment with this horizontal. After 6 we will choose 3 or 1 let us say 1 1 will go from 1 will be connected over here then on this horizontal track and then connected again by a vertical metal wire from here to here and connected wire wire wire will be here as well as here. So, the scope the horizontal scope of this 1 is from here to here just notice that the track for 1 has been like you know we had to choose a new track for horizontal track for 1 we could not layout 1 on the same horizontal track as net number 6 because there would be an overlap and we are assuming that we have only 1 horizontal layer but may be 2 or more vertical layer. So, we cannot have the layout of net number 1 and net number 6 on the same horizontal track because of the obvious overlap. So, net number 1 has to be opened up on a new track net number 3 but similar consideration has to be put on a new track next track number 3. So, we seem to be using 1 track in every such case let us look at the next 1 number 4 no next next 1 is number 5 that is a next 1 in the sorted order and again we have to open up a new track. But now when we look at net number 4 which is next we realize that its scope is from pin number 4 to this pin number 4 and you see that it can be accommodated on the first track itself because the first track now is empty the net 6 has finished its scope and net 4 can now start. So, you see next that net number 4 can be laid out on this on 1 of the earlier utilized tracks specifically track number 1 itself. So, this is how we are kind of now this hopefully the algorithm is optimizing as compared to this picture where we have used 1 track per net we will be reusing some of the tracks for more than 1 nets. After that net number 2 again can be accommodated since its scope is from here to here this horizontal scope is just this much it can be fitted on the on the second track because net number 1 which was laid out on that track is now over. So, 2 so that is over. So, we have laid out all the 6 horizontal tracks of the 6 nets using only 4 tracks as compared to using 6 tracks over here. If we had been less careful we would have used 6 tracks or 5 tracks but optimal 1 this can be shown to be optimum solution because of assumptions that we are making because this particular example does not has only 2 terminal nets and assume that there would not be any problem in laying out the vertical wires they would not overlap. They overlap we can use different layer different vertical layer for the vertical branches if in the absence of such so called vertical constraints this algorithm will be will give you optimal result for set of 2 terminal networks which are to be laid out in a channel. So, and it is more sophisticated variations or more like you know practical enhancements like there is something called greedy channel router GCR there is dog leg router various channel routing algorithms have been investigated and most of the standard text will give you a good treatment of this algorithm. So, the purpose here was just a very sketchy like simplistic overview and next couple of lectures we will have will address the other algorithms for placement on partitioning and timing. So, I stop here