 Ok, jsme jsou všechno výjště uvíšení a tady jsme musíme dělat quad-SPI drive. Příště jsme musíme mít vrátil vzážení datářskou a dělám quad-SPI HAL. Několik, vzážení vyskávů městů je standardizný. Jsou jsou hodiny vždy, které je hodiní s vývodí, které je svojí zvědělá. t.ex. 4-wire mode enabling number of dummy cycles A.T.C. There are most parameters to be set for sending and command in hull structure. User has to set number of lines for instruction, number of bytes and number of lines for address, number of dummy cycles and number of lines for data. Here you can see HAL structure for commands definition. As you can see, there are parameters for each phase of data transfer. Instruction, address, alternate bytes, dummy cycles and data phase. Input values for parameters can be found in file stm32f7xx underscore hal underscore quadispi.h. All parameters should be filled for avoiding uninitialized access. Now I will show you few slides with a practical example how to set up as command parameters. Here you can see chip select, clock and instruction in the snapshot of the memory datasheet. Chip select and clocks is handled automatically by quadispi peripheral and only instruction has to be defined as 6 hexa on one SPI line. Other phases like data, address, alternate byte are not available in this command. Let's move to read status register command. As we can see there is one byte for command and two bytes for data without any addressing. Both phases run only at one quadSPI line. Sector arrays command specifies address, which will be erased. It means that this command has only two phases, instruction and address. Address is 24 bits in this case. For some memories it could be 32, it depends on memory size. The command can work either on one line or four lines, as you can see in the picture. Four lines usage has better performance because the same instruction take less clock cycles. The settings depends on your decision. If you decide to use four lines it is needed to enable quadSPI mode before. Next important command is read operation. Usually memories offers more read operations. In this picture you can see one line reading B hexa command. It uses four phases. 8-bit command, 24-bit address, dummy cycles for a reading and data. Dummy cycles are frequency dependent and ensure enough turnaround time for memory. As I mentioned, memories offers more commands for read operations. Here is EB hexa command for communications on four lines. Command face runs at one line, but others runs at four lines. It increase communication performance. Write operations offers more complexity as well. Here is one line operation, which uses three phases. Command 2 hexa, 24-bit address and data. No dummy cycles needed for write operation. Here you can see four lines write operation. It is almost the same as previous example, but it uses four lines instead of one line for others and data. Command is defined as 38 hexa and it runs still on one line, which is slightly slower compared to QPI write, but no settings of QPI mode is needed. The fastest options for writing data is QPI programming. It uses four lines even for command, but QPI mode need to be set before. Memory contains status register with few indicators. Important flag for us is write in progress bit. It indicates whether write or erase operations are still ongoing or finish it. For that functionality we can use auto pooling mode. This mode automatically uses read status register command in defined intervals and wait until mask and match conditions are fulfilled. As config match and mask must be aligned with memory datasheet. If we know how to compose QPI command, we should create driver in QPI.c and .h files. We decided to standardize away how to handle this part, because as mentioned previously, there is public storage for QPI drivers to be invisible for all of you. We defined a new naming for external memory drivers CSP chip support package. QPI.c and .h files must contain initialization of memory, erase operations, write and read functionality. The functions should have the same name and parameters as defined here in slide. The content of the functions is specific for memory sales type and must be developed by user. Header files should also contain size of memory with the same naming. I have prepared files with full QPI content. In the hand zone, we will just copy this part to the project because writing all QPI commands would take a lot of time. However, you can have a look to QPI implementation and get inspiration for your project. On this slide, you can see content of public storage. Loader files folder is split into two sections because H7 device has access RAM at different address. Both sections contain drivers and linker needed for external loader development. Next folder in public storage is QPI drivers. There is only one memory driver in the folder for now, but it should contain more and more drivers in future. Everybody has access to the storage, so if you write a new driver and be some kind, you can upload it to the storage and make it visible for others. It could be nice cooperation between users. Last folder is QPI testing. MainTest.c file contains routines which checks memory functionality. The routines test memory space with arrays write and read operations. Test binary file can be used later for checking external loader behavior in a stem32Q programmer tool. As the last step of this session, we will upload the binary to external memory.