 Hello and welcome to this presentation of the STM32 Global Interrupt Controller, or GIC. The global interrupt controller embedded inside the STM32MP1 microprocessor provides up to 288 interrupt channels with support of trust zone and virtualization. The application can benefit from dynamic prioritization of the interrupt levels, arm trust zone security extension, and for multi-core product, the interrupt distribution to each core. The global interrupt controller is tightly coupled with the ARM Cortex-A7 processor and provides a dynamic reprioritization of interrupt requests, allowing an application to better serve the incoming events. Most of the peripherals have a unique interrupt line, making the development of the application easier. No need to determine the source of an interrupt during the interrupt handling. In case of multi-core Cortex-A7 processor, each interrupt can be distributed to a single or both cores. GIC also fully supports ARM trust zone security and virtualization extensions. The GIC receives up to 256 interrupts from STM32MP15 peripherals shared between the two Cortex-A7 cores. In addition, up to 16 internal private peripheral interrupts, or PPI's, and up to 16 software-generated interrupts, or SGI's, are managed by each Cortex-A7 core. The GIC signals interrupt to each core with FIQ and IRQ. In a usual software implementation, FIQ is dedicated to secure interrupts. The GIC also provides virtual control and interface for each Cortex-A7 core, helping hypervisor and virtual machine implementation. Here is a list of the different type of interrupt sources managed by the global interrupt controller. Software-generated interrupt can be used to send an interrupt to the other core and private peripheral interrupts are mostly from timers. Note that there is one set of private interrupts for each core, which is completely independent from the other core. The shared peripheral interrupts are the usual STM32MP15 interrupts coming from peripherals, for example, UART. These interrupts are shared between the multiple Cortex-A7 cores and can generate interrupt to one or both cores. Note that an interrupt does not have programmable polarity and can be either rising edge or high level sensitive. Within FIQ or IRQ interrupt routine, interrupt's pending is identified inside the GIC by an ID number from 0 to 287. There is up to 32 interrupt priority levels. GIC includes a mechanism to avoid non-secure interrupt to get higher priority than secure interrupt. Using half of the priority range for non-secure interrupts allows the secure interrupts to use the full range of priority and choosing which secure interrupt could be protected from non-secure interruption. In that case, non-secure software can only see the lower 16 possible interrupt priority levels. Finally, the GIC distributor selects which priority is presented to each core. There is a separate CPU interface for each Cortex-A7 core, which presents either shared or banked register and either secure or non-secure register view. The global interrupt controller fully supports trust zone security and allows a flexible implementation of secure and non-secure interrupts. Virtualization is a system supporting more than one operating system at a time or multiple independent instances of the same operating system. The GIC helps support of such virtualization, for example, by providing virtual interrupts to a virtual machine. For detailed information, please refer mainly to the Arm Generic Interrupt Controller Detector Specification, ARM IHI 0048. Please also visit the MP1 Wiki pages for details.