 Hello and welcome. My name is Jakob and I work with ST Microelectronics as an applications engineer with a focus on power management and analog electronics. In this video I will introduce to you the foundational features and capabilities of the ST PMIC-1 power management IEC. I will also show you how and why we have implemented a complete protective system to defend the STM32-MPU against electrostatic discharge events on our STM32-MP1DK discovery boards. The ST PMIC-1 is a fully integrated power management IEC designed for applications that require a complete and highly efficient power management solution. The device includes a total of 14 power conversion outputs to support both the MPU and multiple peripherals such as USB devices, SD cards, double data rate RAM and more. All output rails are completely protected against short-circuit and overcurrent events to ensure the safety of the devices. It features a digital interface that allows a host processor to control and monitor the application through I2C or through IO pins as well as a non-volatile memory that can be programmed to configure and customize the application to your needs. As you can see in the table on the right the ST PMIC is delivered in three different configurations. The A and B configurations are pre-programmed to easily accompany the STM32-MP1 series application processor versions while the C configuration is typically chosen for bespoke applications. All varieties are anyway fully configurable and the A and B configurations are simply pre-programmed so they can be used straight out of the box. Now when taking a closer look at the ST PMIC-1 we can start with the power conversion. The input voltage range from 2.8 to 5.5 volts allows the ST PMIC-1 to be supplied in multiple usage cases such as from a common lithium ion or lithium polymer battery as used in variables or almost any portable device from a 5 volt wall adapter as found in many home electronics or from 5 volt USB buses such as from a computer or a USB hub. The ST PMIC-1 features 14 separate output rails all of which feature high performance low quiescence and comprehensive protective systems to ensure the efficiency and durability of your application. The 14 buses are comprised of four fully adjustable, highly efficient and precise switching buck regulators. Six adjustable LDOs with high accuracy and good transient response as well as one auxiliary LDO intended to be used as a reference voltage for DDR memory. And one efficient boost converter with a smart BIPA system that can supply up to three USB host ports using the two power load switches. One of which is compatible as a USB on-the-go port or USB Type-C dual roll data port and the other which can power two USB standard host ports. In the digital domain the mentioned I2C and digital IO interface allow a host processor to control and monitor the ST PMIC-1 at all times. This enables you to configure the regulators, switch power modes, handle interrupts, wake-up protocols, manage reset events and enable or disable line protections. To ensure that the ST PMIC-1 can work independently it also features a non-volatile memory that stores values such as the default output voltages, the auto turn on and start sequences, the I2C address and the protective behavior. The NVM also features a lock bit that can be used to prevent tampering. The I2C programming even allows in-system programming to make it easier to integrate the ST PMIC-1 into your application. All varieties of the ST PMIC-1 are delivered in a WFQFN 5x6 mm package with 44 leads and a pitch of 0.4 to provide a good balance between size and ease of routing on the PCB. The regulators are further optimized to use a few parts and low-cost discrete components to reduce the total price while retaining good performance. With three components per DC-DC regulator and only two per LDO your design is guaranteed to be compact. The ST PMIC-1 also features software support and both the Linux driver and STM32 CUBE programmer tools are available online for you to use. We will now take a closer look at the power management starting with the switching regulators. As you can see the four buck regulators have been assigned names to suggest their intended application. Buck 1 is primarily dedicated to supply the core power domain of the application processor. It can output up to one and a half amp with a voltage range from 725 mV to one and a half volt in 31 discrete steps of 25 mV each. Buck 2 is typically intended to supply the DDR memory. It can output one amp with a voltage range from one to one and a half volt in 10 discrete steps of 50 mV each. Buck 3 is dedicated to the VIO and analog subsystem. It can output up to 500 mA and has a wider voltage range from 1 to 3.4 volts in 24 discrete steps of 100 mV. Buck 4 is a general purpose output. It can be used to power any peripherals or for example power the CPU domain on devices that have separate core and CPU domain power. It has the highest current rating of 2 amps and the widest voltage range from 600 mV to 3.9 volts adjustable in multiple discrete steps of varying sizes. Each buck regulator has up to 90% efficiency across its entire range of output. They are optimized for two different operating modes, one for low power and one for high power applications. The PVM of each buck has been synchronized with a 90 degree phase offset relative to the neighboring buck. This reduces the total instantaneous value of power drawn from the supply bus which helps to reduce the EMI generated. The regulators operate with a base frequency of 2 MHz and are based on an adaptive constant on time controller that guarantees excellent transient response and efficiency even in low power applications. Additionally, the regulators are fully protected against overcurrent situations and feature an optional output discharge. The boost converter is a fixed output 5.2V 1.1A step up converter dedicated to supply USB ports with a typical efficiency of 90%. The guaranteed accuracy of plus minus 3.5% in all conditions ensures that it is compliant with the specifications for USB V-buses. In addition to the step up conversion of the input voltage, it also features a smart bypass circuitry that is enabled whenever the input voltage exceeds the output voltage. The bypass circuitry can smooth out voltage transients so as to still comply with USB V-bus tolerances. Like the buck regulators, the boost regulator also features an optional output discharge and is protected against both overvoltage and overcurrent situations. Now for the low dropout regulators. First off, we have four adjustable general purpose LDOs with some suggested applications. LDOs 1, 2, 5 and 6 are general purpose regulators. As you can see, LDOs 1 and 2 are identical in output voltage range and current rating from 1.7V to 3.3V with a current rating of up to 350mA. LDO 5 has an extended voltage range of up to 3.9V and it retains the same current limit of 350mA. LDO 6 also features an extended voltage range but in the opposite direction. This allows for a lower output voltage than the other regulators. The output voltage ranges from 0.9 to 3.3V and it can supply up to 150mA. All LDOs are adjustable in discrete 100mV steps. Moving on, we have LDO 4. This is an LDO with a fixed output of 3.3V and it can supply up to 50mA. This LDO is intended for the host processor's USB physical layer and effectively switches between three internal voltage sources to ensure a valid output voltage in any usage case. The final LDO, LDO 3, has a similar output voltage range to the general purpose LDOs and it can supply 150mA. The unique feature of this LDO is however that it can switch between three different operating modes. It can operate as a normal LDO, it can operate in sync source mode that enables it to support DDR2 and 3 RAM and it can operate in bypass mode to support low-power DDR RAM, in which case it is internally powered by a 1.8V supply. It also features an auxiliary output called REF-DDR. This provides a stable reference voltage for the connected DDR memory. All of the LDOs share the same input voltage range and have a guaranteed max dropout voltage of 220mV at full load. They have an accuracy of plus minus 2% and of course also features overcurrent protection and a programmable output discharge. The two final output rails are the power load switches. The first switch, switch 1, is internally supplied from the boost converter. It can supply up to 500mA to any load. It is compliant with USB on-the-go and USB Type-C dual-role data specifications. It supports VBUS detection to facilitate USB connections. It is protected against reverse current and overcurrent situations. The second switch is titled as a general-purpose load switch. It supports up to 1A and can be supplied either from an external source or even connected directly to the output of the boost converter. The current capability allows it to supply, for example, two USB standard host ports and it also features overcurrent protection. Now we will take a look at the digital interface that allows you to configure, control and monitor the operation of the STP MIG-1. The control interface works according to the VIO domain voltage. The I2C interface works in slave mode. It supports both standard and fast mode transmission with data rates up to 400kVPS. It also supports fast mode plus which can boost the transmission rate up to 1MBS. The interrupt end line is an open drain output for interrupts. It can be triggered by conditions such as a low input voltage or when overcurrent and overvoltage protections have been engaged. The reset end line is a bi-directional line for both the PMIC and the host processor to use to exchange reset signals. Power control allows the user to quickly switch between the two alternate power modes. These can be used to address low power conditions. Typically, the main mode is used for full load conditions while the alternate mode is used for low power conditions such as standby or sleep mode. Wakeup is self-explanatory by name and is used to send a power on signal from the host processor to the STP MIG-1. PUNKEY N is a user power on key. It can be configured to, for example, power on or reset the device from a signal source external to the host processor such as a push button. The inbuilt non-volatile memory can be programmed via the I2CA interface and can be used to set the default output voltage for every buck regulator and adjustable LDO to set the power rank of each regulator so as to define the sequence in which they are powered up or powered down. To enable or disable the PMIG from automatically turning on the power outputs when detecting a rising input voltage. To set VIN OK, which is the minimum voltage required to allow the PMIG to work, and to set the hysteresis value which defines how low the voltage is allowed to drop before the PMIG is turned off. To change the I2C address, it is important to note that this change is immediate and any further communication must immediately rely on the new address and to lock the non-volatile memory using the lock NVM bit to prevent tampering. The non-volatile memory is read automatically before every power up sequence and the NVM content is loaded into the shadow registers to set the control registers with default values for the power on behavior of the STP MIG. As you can see in this table, the default output voltages are different for each of the three varieties of the STP MIG1. In addition to the output voltages, you can see that each regulator excluding the boost has an assigned rank. This rank defines the order in which the regulators are turned on after startup. As you can see, for the STP MIG1C on the right, all regulators are defined as rank zero. This actually means that they will not turn on at all unless prompted to do so by the host processor. A and B have predefined ranks for several of the regulators. At the bottom of the table, you can see the setable VIN OKRISE which defines the turn on value of the input voltage. This is also configurable. We will now take a closer look at the power ranks using an example of a power up and power down sequence. Anything in the top left, we see that the input voltage is above VIN OK, meaning that the device is ready to be turned on. Once the turn on condition has been asserted, the PMIG enters the check-in-load phase. This lasts for 7 milliseconds. Then it engages any rank 1 regulators. It then engages the rank 2 and 3 regulators, each with a 3 millisecond waiting period. And as you can see on the bottom, the rank 0 regulator is not enabled at all until it receives N enabled via I2C. Once all regulators within rank 1 to 3 are enabled, the RESET N signal is de-asserted meaning that it is set high. At the end of the power on state, the turn off state is initiated, for example by the host processor. Immediately RESET N is asserted, set low, and following a 100 microsecond delay, any rank 0 regulators are turned off. The remaining regulators are then turned off in the reverse order from which they were turned on, meaning that rank 3 is turned off first and rank 1 is turned off last. In this slide, we have a complete application example of how the STP MIG 1 can be interfaced with the STM32 MP1. Starting on the left, we see that the PMIG is supplied by a DC source, such as a battery or a wall adapter. The input power is then boosted by the step up converter and provided to the load switches. Load switch 1 is used for a type C dual roll data port, and switch 2 is used for USB STD hosting. Pack 4 is used to supply wireless peripherals, such as Wi-Fi or BLE communications. The general purpose LDOs indicated on the bottom are used to power an SD card reader, an LCD display, while LDO 1 and 5 are used for general purpose activities, such as powering sensors, indicator LEDs, or other peripherals. On the right, going upwards, we see the I2C communication between the STM32 MP1 and the PMIG. Above, we have LDO 4 and box 1, 2 and 3, working to supply the USB physical layer, the IOVDD, the core VDD, and DDR. Finally, LDO 3 and RAF DDR are used to supply the connected DDR RAM. In addition to the discovery boards, we also offer an application board called Steval PMIG 01 V1, which can be used to evaluate the ST PMIG 1 for other usage cases than those given by our boards, such as a standalone case. As you can see, the board allows you to access, connect, control, and measure every output and regulator included in the PMIG. On the bottom right, you can see a list of suggested components that will provide the best balance between price and cost of assembly. We will now take a look at ESD protections and filters. The STM32 MP1 DK2 discovery board allows you to easily develop applications with the STM32 MPU. The board includes an embedded ST-Link debug tool, one Ethernet connector, one USB Type-C ODG connector, four USB Type-A host connectors, one HDMI transceiver, one stereo headset jack with microphone, and one microSD connector. In addition, it features two GPIO connectors for connecting Raspberry Pi shields. To complete the system, the discovery kit also includes an LCD display with a touch panel and the capability to communicate via Wi-Fi and BLE. All of these connectors and onboard devices are equipped with ESD protection devices. I will first show you what ESD is, how it is generated, and which effect it has on integrated circuits before we take a closer look at the protective devices we have implemented on the STM32 MP1 DK2 board. ESD, or electrostatic discharge, is a swift discharge of electric current between two electrically charged objects that occurs when the objects are touched together, such as when connecting devices using cables or onboard headers. One of the most common causes of ESD events is static electricity. Static electricity is the collection of electrically charged particles on the surface of a material that typically occurs when two materials are rubbed together and then separated, a phenomenon called tribocharging. Various materials have a tendency to either give up electrons and gaining positive charges or attracting electrons, meaning that they gain negative charges. This builds up a charge that is just waiting to discharge and cause an ESD event. As you can see in the table on the right, common situations in your office, lab or factory floor can generate tens of kV ready to discharge into the devices you are handling. Electrostatic discharge is always a potential cause of failure for integrated circuits in your product. These failures are called electrical overstress or EOS failures. They can result in damages such as silicon melting, oxide punch-through, junction damage, metallization damage, or even degradation affecting the long-term reliability of your electronic system. A survey from the EOS Industry Council shows that 30% of customer claims are due to ESD or EOS, making it the single largest contributor to device damage. Furthermore, as new production technology allows us to make smaller features in the silicon, the ESD susceptibility of the components also increases and ESD protection becomes more essential. ESD events are defined in multiple standards and cases. On the left side of the chart, we can see component-level ESD conditions. This definition is in place to ensure the manufacturability of integrated circuits. These standards reproduce ESD during manufacturing processes, which means the ESD risk is mitigated by using specific equipment in a controlled environment for manufacturing. For example, technicians can wear anti-static shoes and there are de-ionizers to avoid the charging of the air. Each person or equipment must be connected to ground in order to allow a safe discharge path. The related standards are HBM, the human body model. This simulates electrostatic discharge caused by discharge when a person handles the device. MM, the machine model. This simulates ESD caused by a machine discharging through the device to ground. CDM, charged device model. This simulates the ESD due to mechanical device handling, such as when the device slides along a surface, such as in the factory plant. The ESD protection, according to these standards, concerns any integrated circuit and is also known as un-chip ESD protection. The second case on the right side is related to system-level ESD and this is the case that occurs in our everyday life, such as when you are walking across a carpet or vinyl flooring or when handling plastic wrapping. The IEC 610042 standard simulates a complete system that may be subjected to ESD. In this case, the only way to manage ESD events is to add dedicated ESD protective devices mounted directly on the PCB and placed in the critical discharge path. Now, as we return to take a closer look at the board, you can see that we have highlighted the ESD protective devices which have been equipped to all of the exposed connectors. In addition to the connectors, we have also added protections to other susceptible areas, such as the user input buttons and the SD card slots. The protections added to this board ensure system-level protection in compliance with the previously mentioned ESD system-level standard IEC 610042. Thank you for watching this presentation on the STP-MIC-1 Power Management IC and ESD protections.