 Welcome to this lecture on VHDL in the course digital system design with PLDs and FPGAs. The last lecture we have gone through the use of multiple architectures, two models of description one is you know data flow model and behavioral model. So let us look at the slide when you have the multiple architecture for a single entity it can be used you know you can have a scenario where you write a quick code for simulation or another architecture which is kind of after the simulation you can do it for synthesis. Maybe you write one architecture for minimum area and the one for maximum speed one could be for FPGA one could be for PLD or ASIC and so on. And we have seen the design flow we start with the VHDL source code which is functionally simulated the code is simulated not the circuit to remove the logical syntax errors and iterate here then you go for synthesis where the logic circuit is created and you can do a logic simulation if you correctly code if you correctly write the synthesizable code this step may not be necessary. So you can do a logic simulation which is a both these simulations are not delay because it is not mapped to the device set then once you do the synthesis you can go for the process of place and route or fitting place and route is called PAR and you give IO constraints and timing constraints do quick static timing analysis depending on the delay of the block and when you iterate there and when everything is okay you do timing simulation which might take time for complex circuits then everything works fine then you can program the FPGA. So basically you have an editor you have a synthesis tool, constraint editor, a PAR tool, a programmer, a static timing analysis tool and a simulator which does all these you know functional logic or timing simulation. So these are the kind of the tools we use and we have seen the data flow model the first code as an example we have seen is a data flow model where it shows the data flow this is a input and you know the output gets assigned and this use a construct called venal statement which is used in the concurrent body. So this is a concurrent body everything in the architecture statement region is concurrent and this is a concurrent statement there is another statement called with select which we will see later. There is another way of writing using the logical kind of operators as I said this can be cumbersome when the data size is large and so here even if whether it is 3 or 31 it does not matter this works so this is very concise you need not worry about the circuit you end up with these are very simple thing to synthesize. So the synthesis tool will make sure that whatever you have written the equivalent circuit depending on the device in an optimal way is implemented. So that is the data flow model and we have talked about the concurrency as I said there is an issue like it is not like unlike the sequential languages when you write some statements in a specific order in a sequential language one after the other is executed but when you simulate basically simulate a VHDL statement sequentially written concurrent statement like this a top to bottom evaluation will not yield the correct results. So the simulator has to resolve concurrency from the sequentially written code because here it is written in the opposite of the data flow. Data flow is from A, B to X, X to Y, Y to Z we have written in the opposite way so Z and Y will be wrong X will be the correct thing if you do the top to bottom evaluation. Those simulators job is to resolve the concurrency from the sequentially written code but it is not a big issue for the synthesis tool because the expressions are there and you know whichever order it is written does not matter you end up with the same circuit. So in this case at least for in this case the simulators has a hard job than the synthesis tool. We have looked at the behavioural model where we use everything else is same where we use a sequential body called process and process as a sensitivity list we put the inputs there when anything changes in the input it computes from top to bottom once and it uses sequential statement like if then case when and all that. And before the begin you can declare the variables you can declare constants you can define procedures or function which are visible to the body. So and you have a problem if you miss something in the sensitivity list because here you see in the statement there are 2 inputs but if you do not write both inputs then the simulator will give a behaviour which the synthesis tool would not be able to kind of you know produce because synthesis tool does not bother about the real time behaviour it looks at the code and generate the circuit. The code say if a is equal to b equals get 1 else equals get 0 so it just create an equality comparator but the simulator simulates an equality comparator which works only when a changes if b changes next time a changes it works correctly if b does not change till the a changes otherwise if the b changes it does not compare you know something like that. So there is a problem a compatibility problem with the simulation and synthesis the solution is to write all the input signal in the sensitivity list and some tools warn you and if the tool does not warn you it is a dangerous thing because you simulate and see some behaviour and this in a complex case sometime it can be in very simple case you will be able to identify but in a complex case it can create an issue. So one need to take care of this particular issue of missing signals in the sensitivity list and as I said there is nothing great about using processes do not get kind of you know worried about this word processes if you have a block with inputs a b c you write a b c in the sensitivity list you use if case loops etc to define the behaviour of this output in terms of a b c that is all what is required. As I said when I say write the input signal in the sensitivity list little more detail is required maybe today's lecture will throw light on it and we will go ahead and we also said when you have multiple processes both are concurrent say you have 2 blocks they share an input called a so you write 2 processes and if a changes both will be computed for the same event okay is not that the simulator cannot compute at the same time need not be but if a changes at 100 nanosecond both these computation will happen for that particular 100 nanosecond event that is the meaning of concurrency. So let us go ahead and let us come to today's part and here we see a model of description called structural model of the VHDL code which enables us to do the hierarchical design or the top down design and we have seen already how we have designed the CPU top down you know we put a black box CPU say level 1 it was an interconnection of various components. So we will see how that can be done in VHDL using the structural code that is a basic idea. So when you have a top level entity which is built up of the black boxes from the level 2 or the bottom level components then what is done is that you the top level entity you give a name as usual you define the inputs and outputs okay. Now the game is that we are not going to describe the behaviour of the circuit but we are going to say this entity the architecture of this entity is composed of the interconnection of various components that is what is going to be stated in the architecture statement region and for that we need to say what are the components used okay. So maybe you take these two components they may be same components okay you can have a same component instantiated multiple times in an architecture. So you have to declare in the architecture declaration region before the begin the component name its inputs its outputs and the data type exactly like the entity of that component has to be repeated. The idea is that you are going to put another component and you are going to connect using some signal and you know that the VHDL is a strict data type checking language. So if you are connecting an output to an input if output is of the type standard logic then input also has to be standard logic and this wire or the signal connecting them should be of standard logic. So we have to declare the distinct components we are using in the for the interconnection in the architecture declaration region all of them and we also have to you see this signal this is not part of the input or output. So we have to declare that signal it is called signal which has no direction because signal connects some output to input one or two inputs one output to one or two inputs normally unless you use a tri-state gate. So the signal does not have a direction but it has a data type and everything has to match okay. So the game is you define a top level entity with input output port in the architecture declaration region you declare the components essentially it is name, ports, direction, data type everything various components and what are the internal signal you are going to use that has to be declared because that is not part of the input or output that has to be declared what is the name what is the data type and when you come to architecture statement region you say how these components are interconnected using this signal or you can say we define the net list of this interconnection okay. We say the component one particular output is connected to the component two particular input using the description language that is the basic idea. So to make it clear let us take an example we will take the same example okay. We will take the equality comparator we have you know we have described using the data flow model and the behavioral model. So we will use the same thing and you know it is a 4 bit equality comparator. So it needs to check the equality of all the pair of 4 bits A3 equal to B3, A2 equal to B2, A1, A0, B0 and so on okay. So this equality is checked by exclusive NOR gates and the output is going to an AND gate if all are 1 the output is 1 okay. So we have two distinct components we have a two input exclusive NOR gate and four input AND gate okay. Now we have only two components but this particular two input exclusive NOR gate is instantiated four times but we need to declare only once and AND gate similarly we have a four input AND gate which is declared once instantiated once. But mind you we have some signals which is connecting the output of XNOR gate to the input of AND gate. So these are indirect signal this need to be declared okay. So we have four signals this 1, 2, 3, 4 that need to be declared. So we are going to use give a top level entity of the equality comparator. In the architecture declaration region we are going to declare a component exclusive NOR and AND gate we are going to declare four signals and in the architecture statement region we are going to show this component will be instantiated four times this one time and we will show the connections of the wire connection. That means we will say A3 is connected to the first exclusive NOR gate first input B3 is connected to the second input of the first exclusive NOR gate. The first exclusive NOR gate output is connected to the first input of the AND gate and so on okay. We will see how that is done. So let us go to the VHDL code. So you see the entity part is exactly same we have the library declaration, the package use statement entity exactly similar to the previous one A and B are 4 bit vector equal is a single bit vector okay. When it comes to the architecture part you see before the begin there is an architecture declaration and there we are going to declare components and the signals and you see the component this component is XNOR gate this one and the port is I1, I2 in standard logic two inputs of type standard logic O1 colon out standard logic one output which is standard logic and you see normally in architecture entity there is an is syntax but for some reason VHDL does not have component name is there is is missing so do not write is it will give an error and here the AND gate is declared so component AND4 which has four inputs and one output so the port I1, I2, I3, I4 in standard logic O1 is out standard logic. So normally when you write the description of the AND gate and the XNOR gate this component declaration is exactly like the entity. So it is enough if you write the component entity and architecture you copy paste the entity here change the entity and N to the you know entity to the component and this entity name to the component and remove the is then you will get it and this is similar to in a C code when you write a C language program and use a function if the function is elsewhere then you write a function prototype okay. Many a times that you will find in the header file which then checks for the type of argument past and all that this is something similar because VHDL is a strict data type checking language so ultimately we are going to use instantiate this component and connect some wires to it. So the tool will check whatever the wires you are connecting is of the same data type so that need to be here you know that is why this component part is here we will see how to write a component in the library and use it and all so on. But the basic purpose is that and this component need not be as part of this particular the file it can be elsewhere it can be in a library or it can be elsewhere it does not matter. Now before we declare the signal the syntax is signal, name and the data type. We have four signals which are of the same type we use you know we specify in the same statement signal in 1, in 2, in 3, in 4 colon standard logic okay that means that we are naming this as in 1, in 2, in 3 and in 4 that is a game. So we have declared the two components we have declared the signals now we are going to instantiate this four times, instantiate this one time and going to interconnect them that is what is going to be done. So this is what is shown here we connect a3, b3 to the first one, the output is in 1, a2, b2, into a1, b1, in 3, a0, b0, in 4 and the AND gate get this in 1, into in 3, in 4 and the equals. So the syntax symbol you give a label some label does not matter colon the component name and we say the port map that means the actual formal ports which we declared as i1 and i2 is mapped to the actual port. So we are going to specify a formal to actual mapping that is why it is called port map and we say a of 3, b of 3 and into 1. Because we have declared this as i1, i2 and o1 in the same position so we are associating a3, b3 and into 1 that is this one. Similarly c2, x02 port map a2, b2, into a1, b1, in 3 that is this a0, b0, in 4 that is this one and ultimately this AND gate which gets in 1, into in 3, in 4 and equals in 1, into in 3, in 4 equals in the same order okay. So this is called a formal to actual mapping by position or we can say we are associating the actual to the formal you know in a positional way. So it is called positional association. So you have to remember the order like you know that the AND gate inputs can be in any order but then at least you should remember where the input is, where the output is. Suppose if we had specified in the declaration equals you know at the beginning then we have to you know bring the equals so here you know. So if the o1 was at the beginning then equals has to be written at the beginning. So this is kind of done, this is how the structural description happens, instantiate the components and formal signals are mapped to the actual signal by position. It is very simple there is nothing you know great about it and but ultimately now we say that this can come from a library or it can come from a different file. Ultimately there has to be description of the XNOR gate and the AND gate for it to happen. It may be in the library already compiled, may be in the project in another file but it has to be written sometimes by somebody okay. So I am for completion sake I am showing that. So we have the component XNOR 2, library close, entity, port I1, I2 and o1 and architecture we have very simple statement o1 gets I1, XNOR, I2 and that is the end of the architecture. Finally you have an AND gate which is for input I1, I2, I3, I4 in standard logic, o1 is out standard logic. In the architecture declaration statement region we have o1 gets I1 and I2 and I3 and I4. So it is simple as it is. So if you write this and you know you compile it, this will be same as the behavioural code or the data flow model and so on. At this point somebody might ask is there a difference between the earlier code and this code which gives a better circuit. At least for the simple, very simple cases like this it does not matter at all. But when you write a very complex circuit using behavioural the data flow and the structural code you can get different circuit. It depends how you understand, how you describe and things like that. So we cannot say but if you follow the strict practices what I am going to teach you then you can be sure that you will get the kind of the expected circuit with maybe some kind of optimisation in all three cases. You need not worry at least in simple case you can close your eyes and choose. There is no need to frankly if you are making an equality comparator there is absolutely no need to write a structural code just illustrate because if I take an example complex example it runs into pages and just to illustrate I have used a very simple code but you do not do that. There is no point in making a ripple adder or a equality comparator using a structural code when you have complex design which is partitioned into multiple pieces then those partitions are combined in a structural code you know top level or the level second level and so on. But when you come down you can still use the behavioural and the data flow description when you really describe the known high level functions as we discussed like MUX, DMUX, encoder, decoder, adder, subtractor all that can be described behaviourally or in a data flow model and when we come up when you put it together use a structural coding that will be easy to kind of keep track of then again come you can combine them in a behavioural way but then it is it can be complicated to track it is easy to use a structural coding at the top level when you connect the complex blocks together ok. So let us move on let us see some kind of this let us look at this component instantiation. The way we have done the positional association is like X02 port map then I1 is mapped to A3, I2 is mapped to B3 and O1 is mapped to I1 a positional association. But when you this is ok if you are writing the code then the code is in the same file suppose you have written the X02 code that is in the same file you can scroll down and check the order of the formal ports then you can map it correctly. But when somebody has written a library component in a library it is very difficult to keep track of the order but they can give an input output table where the input signal name and the data type is described and the function is described. So it will be convenient if you can forget about the order of the ports we can say what is the formal port name and what is the actual port name association can be specified explicitly that is called named association which is the most useful way of you know doing the port map. So that is like this you know you can say for the previous case this case you can say X02 port map O1 is mapped to IND1, I2 is mapped to B3, I1 is mapped to A3 exactly similar to this you do not have to keep any order you correctly say which formal port is mapped to which actual part that is it ok. So that is the named association the most useful way of you know describing the component instantiation. So let us move on you know that when you write some software code like if you are a computer science student or you have written some serious software one important thing before you write the code is a data structure ok. So algorithm you have the proper data structure if you define then the code will be very easy you can have an elegant the C code if the data structure is correct where you are supposed to use an array if you use a kind of distinct variables set of distinct variables the code will be very clumsy. So similar to that in VHDL if you define the signals in a proper way the code can be very elegant and concise. So I am going to show the same structural code we have written I will introduce a slight change and show you how it can simplify the code how it can make elegant you know make the code elegant. So let us move on so we have declared earlier the internal signals as four distinct signals called int1 int2 int3 and int4 ok. You remember that suppose instead of that I am going to declare this signal as a 4 bit vector ok or 4 bit array or whatever 4 bit bus ok. So I am not calling int1 int2 int3 int4 so I am calling the signal int ok which is standard logic vector 3 down to 0. That means you have an int of 3, int of 2, int of 1 and int of 0. The moment I write like that then what I do is that earlier code was written like this a3 b3 and int1. So I could write now instead of that I have changed the declaration to a bus which is 4 bit. Now I am going to change the you know description which say x0 to port map a of 3 b of 3 and int of 3 a2 b2 int2 a1 b1 int1 a0 b0 int0. In the 4 you know the component instantiation or the XNOR gauge and in the AND gate the inputs are int3 int2 int1 int0 in any order and the equals ok. Now you see here this comes neatly you know you have 3 3 3 2 2 2 so you can write something called for this 4 statements you can write a loop called generate loop. So that is written shown here for i in 0 to 3 generate c x0 to port map a of i b of i int of i. That means it goes from a0 b0 int of 0 a1 b1 int1 a2 b2 int2 a3 b3 int3. You might ask what happened to the label we are not giving c of i you do not need to give you just give c you will automatically get c0 c1 c2 c3 ok. Do not worry about the label and ultimately you have to write the instantiation of the AND gate. Now mind you this is not a loop in a conventional sense of the sequential language because in a sequential language you know something is kind of executed one after the other. But this is just a short form of writing it explicitly when the compiler tool see this it will replicate it 4 times like you know a0 b0 int0 up to a3 b3. So it is a very concise way of you know generating this statement. So if you take care when you write the code when you have something replicated with some symmetry it has to be symmetrical and a proper definition of the signal can help you in getting a very simple concise code and which is easy to kind of understand otherwise you have to suppose you have something replicated you know tall times then you have this issue ok. So you can think of doing this for suppose you have a ripple adder where the full adder is replicated 8 times you can write a generate loop. You might need to define the signal the carry input and carry output you know that need to be taken care but that can be easily taken care. So that is one example of this generate loop you can definitely write a generate loop for an 8 bit ripple adder using the component as a full adder. But suppose if you use a carry look at adder that is going to be little tough you know because in a carry look at adder is not symmetric when you move from 0 to 7 it becomes exponentially bigger and you can do that you can write a loop but probably not a generate loop maybe we will see what to be done when you go ahead. And one more thing about instantiation when suppose you are instantiating a component and one of the output is not connected ok. Then when you instantiate suppose see we are using a 4 input AND gate or you say equality comparator with 3 output one is equal to one is greater than one is less than and we are using only equal to in the instantiation. Then when you come to the greater output and less output when you instantiate you have to say since it is not used you have to say open and similarly some inputs are like you have using and in some case you are using only the 3 inputs of an AND gate. Then one of the input has to be tied to you know 0 the inactive level depending on whether the function is AND or OR ok. So you have to properly tie it to the appropriate logic levels when an input is not used otherwise things would work because we are describing the hardware so that need to be taken care. So let us so that is about the different models of description the structural coding is what we have looked at basically we instantiate we declare components declare internal signal instantiated and interconnect them by describing the interconnection using the internal signals and ports and if you elegantly define signals you can you know use the kind of concise elegant generate loops for a you know kind of when there is quite a good symmetry you can work it out it becomes concise. And if an output is not used you have to say open input is not used then you have to pull it up or pull it down depending on the function of the circuit to make it inactive. So let us move on now that is the three different models of description. Now let us look at the simulation ok I do not know whether you have done any digital simulation maybe near the undergraduate you have done the analog simulation using SPICE and so in a SPICE simulation suppose you have a system maybe a filter let us take an example of a low pass filter and you give some input say maybe some trapezoid waveform and you will definitely the low pass filter depending on the cutoff frequency is going to smooth it out you will get a triangle wave or a sine wave depending on what are the filters design. But in a you know that in a SPICE simulation it is going to divide the whole period into minute intervals ok it need not be uniform because you know in a trapezoidal waveform maximum information is in this kind of slope all the harmonics the frequency content comes because of this kind of rate of change. So there will be lot of division lot of steps there when it is stable maybe less steps. So the SPICE is going to divide into interval and there will be computation of the input with the system transfer function to generate the output ok. So that is how the analog simulation or the SPICE simulation is done. So let us see how it is different for a digital circuit ok. Now look at a digital circuit so you see here I have shown some like you can imagine this is a digital system now and we are giving some input to the system ok. Now you see here this input is changing like that and this one is changing like this ok. Now suppose initially at the first step the simulator take these values 0 and 1 and compute the output but you know the moment it is computed there is no point in dividing this into minute intervals and compute it because it is going to be stable. Because the digital system is binary but here you see when an analog signal changes the value moves from all the values are important it may be going from may be 0 to plus 15 volt each voltage is important but in our case either 0 then 1. So there is no need to compute once 0 1 is computed the next computation need to be need to happen only here because the input signal is changed from 0 to 1. So now you compute here at this point 1 1 the moment you compute till any change happens there is no need to compute because it is going to remain stationary. So as far as digital circuit is simulated, digital simulation is concerned whenever there is a change in the input at that point the simulator need to compute ok. That means whenever we say whenever there is an event on any of the signal at that time the computation should happen ok. So the in digital simulation is an event driven simulation whenever there is an event on any of the signal then the simulator has to compute otherwise nothing to do ok. So events trigger the computation and events can be on the inputs maybe event happens like you give the inputs to various input signal then you have to compute but because of the input something can change internally at that time also that should trigger a computation. So in digital circuit unlike the analog circuit we use event driven simulation like you take a combinational circuit then we have to simulate by you know it is an event driven simulation. Now let us come to the sequential circuit now when you have a sequential circuit suppose the input is changing quite a bit suppose we give a clock which is say of frequency say 100 megahertz then the duration is 10 nanosecond. But maybe all the inputs coming to this register say we have a register combinational circuit and a register here the input is changing say every 1 nanosecond. But we know that this flip flop is going to be large every 10 nanosecond. So there is no point in computing the simulator to compute every 1 nanosecond ok. So in principle for a sequential circuit you can compute on the active clock edge and you can get the value and that is called cycle base simulation. Every clock cycle active clock edge you can do the computation definitely you will miss a lot of things because of maybe that there could be a lot of changes happening here. And unless there is all computed the in between things can be lost but then this is a very quick way of simulating. You do not simulate you know every time the input changes when the clock comes just before the kind of that whatever is the stable input that time only you need to compute. But you might you know you might not be able to estimate the power dissipation and things like that in the simulation or something will be missing but it does not matter for sequential circuit because updation happens only on the clock edge. So the cycle base simulator simulation can be used in sequential circuit so that is a different type of simulation and in simulation there is a notion or a terminology we use simulation time ok. Now you should have some clarity on that first of all it is not real time ok it is not that it is a time of the day or some kind of clock which is running which indicates the real time ok that is not the simulation time. So real time is not simulation time it is not even the time taken by the simulator to compute something say you say you have given a complex circuit for a timing simulation it takes 3 hours to simulate whatever you have given that is not the time taken by the simulator is not the simulation time. Simulation time basically is the time at which the events happen ok. So when you say at 100 nanosecond an event an input A changes then we say the simulation time is 100 nanosecond ok. Then the simulator will start some computation which might take any amount of time like at 100 nanosecond an event happens and simulator computes maybe it will compute in few nanosecond or microsecond or millisecond or hours or day it does not matter it might take a day for the computation of the 100 nanosecond event if the circuit is complex ok. Now after the day everything is done if the next event in the queue is 200 nanosecond the simulation time now goes from 100 nanosecond to 200 nanosecond ok as far as digital simulation is concerned. Because it is event base the next event in the queue in the order is 200 nanosecond the simulation time goes from 100 nanosecond to the 200 nanosecond. So that is the simulation time do not confuse. Now I am giving a very kind of lucid explanation for you to understand the concept I am not going to be very precise I am going to avoid all the terminologies. You can go back to some text book there are lot of you know the names the terminology which is used with regard to simulation I am avoiding everything. You can refer to the reference book and learn all that but it could be confusing for a beginner to go through that I am telling you the crux of the matter in a very lucid way so I cannot be very kind of precise but I am trying to explain the concept in a clear way hopefully you can understand and very important is that events are ordered in the chronological order or in the simulation time that is what I mean is that suppose you are trying to simulate a circuit and you have given say you have an AND gate you are trying to simulate and two inputs are there. Say you give some waveform which changes at 100 nanosecond, 200 nanosecond, 250 nanosecond and 300 nanosecond the simulator will you know order the events like 100, 200, 300 like that you know in the order. But suppose this AND gate is driving another OR gate the AND gate output is driving another OR gate now because of change in the input of the AND gate 100 nanosecond output changes may be after say 101 nanosecond okay. So when the simulator computes earlier simulator had say 3 events at the input of AND gate 100, 200 and 300 but when it simulates it find that the output of the AND gate because of the 100 nanosecond change has changed at 103 nanosecond. So now it has to add an event between 100 and 200 at 103 then only the next OR gate behaviour can be simulated properly. So that is what I mean the events as it happens like when the simulation happens may be there of you give some inputs some events and it is ordered properly. But the simulator as it simulates new events happen in the internal signal that is pushed in at the appropriate place in the correct order and one by one the input is taken and simulated. So that should be understood the best thing is that you draw some two or three level circuit and imagine some input and you try to compute and order it in the proper way then you will understand it very it is better you yourself work it out I could have shown a picture maybe as we go along some pictures will be shown which is related from there you can grasp. So that is the idea of simulation time so do not get confused and there is some the most text book will talk about a simulation cycle basically it shows a resolving the concurrency by sequential computation ok. And they will call you know describe something called delta delay we will see that in a moment ok. So let us move on let us see how the simulator simulates the sequentially written code or the concurrent behavior is simulated properly. So please have a look at the circuit which is shown here. So here we have a very simple circuit an AND gate and NOR gate and AB is going to an AND gate and the output of the AND gate is x, x is x and c primary input is going to a NOR gate which is output is a y and AND gate has a delay of 3 nanosecond and the NOR gate has a delay of 5 nanosecond. And we know that the AND gate 1 1 is 1 for the NOR gate if any input is 1 the output is 0 because it is opposite of OR gate. Now we have not learned about how to specify the delay in VHDL but this is the way to specify it. We are writing the description but we are not writing the statement concurrent statement in the order of the data flow data is flowing from AB to x, x and c to y. But we are going to write this part first and this part second say y gets c NOR x after 5 nanosecond that is this one. And this is the way to add a delay the model the delay in VHDL only for simulation. Just like if you write a statement like after 5 nanosecond definitely you are not going to get a NOR gate with 5 nanosecond delay. If you give it to a synthesis tool it is going to generate some circuit like this ignoring this is not going to give any delay or it gives if you go to FPGA it will map to some circuit whatever may be the delay of the circuit you get it okay. This is not for synthesis it is only for simulation but if you simulate this circuit will definitely show the output will come after 5 nanosecond delay okay. Now x is A and B after 3 nanosecond. Now you see that the y is written first and x is written after that. So the order of the statement is opposite to the order of the way the data is flowing. Now normally as in sequential language simulation if the simulator looks at the like if there is an event on A it computes a y first then x then nothing is going to happen you know because the y say c NOR x after 5 nanosecond whatever was the old value of x is used for y computation. So x is computed and where the new value of A is used and x is correctly computed y is not correct and you can imagine what happens if you have a 5 level circuit and everything is jumbled up okay. So this is a little bit hopeless situation we have to make the simulator has to make some sense out of it okay. Now we cannot say that you look at the order in which the data is flowing and rearrange the statements and so on. This won't work definitely because you can have a feedback okay. So when like suppose you have something one more level and the output is going back to the input then what is the order when there is a feedback there is no order it is like you go to a stadium where a running race is in the progress okay. You go you know people have a running say a long distance 10,000 meter running in a 400 meter track and you go in the middle and if you look and you might guess saying that somebody is in the front maybe you will imagine the tail ender is the top end like that you know. So similar thing when you have a cycle you cannot decide which is the first. So ordering it in a proper way is impossible. So but if you think it is very easy because you know that the computation start because of an event. If an event happens on A then the best thing to do is instead of going from top to bottom look at the right hand side of the assignment wherever there is A you compute that. So that is a game and there could be multiple statement with A it does not matter. Suppose the simulation time is 100 nanosecond at 100 nanosecond you compute x and there may be an z with A you compute z really does not matter okay whatever I am going to show you is a simple case but that can be kind of interpolated to a more complex case only you need to work it out okay. So the rule of resolving concurrency is very simple look at the right hand side of the assignment wherever there is an event and compute that okay. Now you take this simple case let us assume that A is changing at 100 nanosecond. So suppose initially A was 11 the x is 1 so A is changing from 1 to 0 then look at the simulator will look at the right hand side there is an event on A and look at the right hand side here there is nothing so this need not be computed. So A changed at 100 nanosecond so it will compute new value of x and it will assign at 100 plus 3 nanosecond 1 or 3 nanosecond the moment that happens now some signal has changed. Now again the simulator will look where the x has changed at 103 nanosecond. So what the simulator does is that the current simulation time is 100 nanosecond and there is a 100 nanosecond event it has computed some signal you know some assignment for 103 nanosecond. If nothing else need to be computed for 100 nanosecond it will keep the event in order so suppose the next event on x was 200 nanosecond. Now since there is a sorry the A is 200 nanosecond since there is an event on x at 103 nanosecond it will look at the right hand simulation time is forwarded to 103 nanosecond it will look where x happens and you know compute the y and that will happen after 103 plus 5 nanosecond. Again it looks if there is anything remaining to be computed for 103 nanosecond and proceed for the next simulation time 108 nanosecond and so on ok that is how the simulator resolve the concurrency. It does not matter, it does not matter however many statements are there whether there is feedback in whichever order and instead of the engage there are very complex circuit this game works you know anything can be easily the concurrency is resolved by very simple method of looking at the right hand side of assignment where the event happens that is computed and new event happens that is ordered properly and it proceeds. So that is what is shown here so we have at the time 0 A and B are 1 so x is 1 c is 0 so because of x 1 y is 0 now at the 100 nanosecond it remains there A changes from 1 to 0. So the moment that happens this A appears at the right hand side x need to be computed so x is assigned value because A is going from 1 to 0 x will go from 1 to 0 but that happens at 103 nanosecond and y remains same because at 103 the y y y is you know there is no change in the x at this point at 100 nanosecond so y does not change. Now since there is nothing else here to compute at 100 nanosecond the simulation time moves from 100 to 103 and there is an event now on x that will you look at the right hand side that will trigger a computation for y and that you know that is basically 0 nor 0 which is nothing but 1. So the y will change from 0 to 1 which is assigned at 103 plus 5 nanosecond 108 nanosecond since there is nothing remained to be computed at 103 the simulation times move to 108 nanosecond and everything is stabilized. So if you put a waveform this comes very cleanly so basically the game is about resolving the concurrency the issue is order of the statement will not match the data flow the order may be different and the solution is an event driven computation and you look at the right hand side of assignment and one after the other you compute and that might trigger the further events and you order them properly and you know then you treat them one by one everything works properly if you have any doubt you can really you know I have definitely shown some very simple case you can introduce say like event on A at 100 nanosecond at 110 nanosecond 120 nanosecond you can even think of a scenario where A is changing at 100 nanosecond and also at 102 nanosecond before even the x changes ok. So you think really what happens you know you try to work out such a situation that will bring clarity to your thinking and so this shows essentially what I have told is that how a simulator resolve the concurrency from the sequentially written statement might it is a very simple idea is not a very complicated idea but the simulator may have to compute quite a lot a lot of computation need to be done but the idea is very simple whenever there is an event look at the right hand side compute those statement which is an event assign the output order the events sequentially properly and then when every computation at the particular simulation time stabilizes go to the next event next simulation time and keep computing that is a basic idea. So with that I try to complete today's lecture the second part of the lecture shown we have discussed the simulation how an spy simulation happens for analog circuit by you know kind of discretizing the signal at various intervals depending on the need of computation but in digital circuit you do not need to kind of you know introduce intervals wherever whenever there is a change in the inputs that need to be recomputed. So the events whenever there is an event driven simulation for sequential circuit basically you can do whenever on the cycle based simulation on the active clock edge that will reduce a computation and we have seen a simulation cycle how a simulator resolve the concurrency in the case of timing simulation ok we will in the next lecture we will see how that happens in a logic simulation where there is no delay that will definitely bring more clarity to the game. So I stop here please go back and revise whatever is done refer to the textbook to get hold of the terminology used because I have avoided to explain the concept in a very simple and lucid way. So please revise refer to the textbook thank you and I wish you all the best.