 So, we continue our discussion on the metal semiconductor contacts and metal source drain junction MOSFETs. So, we discussed last time that in the case of the MOSFET with junctions, P N junction as the source drain contacts, the when applied gate voltage, the entire barrier height at the source end reduces by twice that. So, because of that electrons are able to inject across that, that is the electron distribution in the N plus region. Whereas, in the case of metal semiconductor contact, the metal, the barrier to the metal 5 B N does not change. When I apply voltage across that by applying gate VGS plus, in fact, it is this potential barrier, it is changing on the silicon side, not this one. So, as a result, the number of electrons which are available for transport from the metal to semiconductor limited to the 2-ose electrons which have energies above the 5 B N, that does not change. Whereas, in the this type of when there is a N plus junction, N plus P junction, that barrier itself changes by twice 5 F, that is the difference. So, what we see is, if you want to have a large supply of electrons here, the 5 B N should be small, barrier height should be small. That means, it should make, ideally it should make a atomic contact on to this channel. And of course, the electrons which are injected here can be rolling down in this, because of voltage drop in the channel, it will be connected. The current will be limited by the supply available here. So, you need to reduce the barrier height 5 B N. So, what one immediately think of is 5 M minus chi or N type material will give you high barrier height, 5 M greater than chi. But, if 5 M is small, then it will give me contact ideally. But, what we have seen is, the metal semiconductor contacts, the barrier height on to the N type material, 5 B N is given by this relationship. Experimentally, one could fit it into this type of curve. So, here you can see, when gamma equal to 1, what is gamma will see shortly? When gamma equal to 1, gamma is between 0 and 1, and gamma equal to 1, second term is 0. When gamma is equal to 1, 5 B N is 5 M minus chi. That is ideal. So, if you vary the 5 M, you should have the variation in 5 B N, but we are not getting that. In some cases, we get 5 B N constant independent of 5 M, when the freshly cleaved surfaces. So, this 5 naught is actually the, we discussed earlier the neutral level. It is the energy difference between the neutral level and the valence band or silicon and gallium arsenide, that is E g by 3. And in germanium, it is equal to 0.09 electron volts. Band gap is 0.66 electron volts. This is very close to the valence band, this 5 naught. We will see it more about that now. So, gamma is called the pinning factor, and it varies between 0 and 1. The value depends upon the surface condition. Gamma equal to 1, expected from first order theory, 5 M minus chi. 5 B N is 5 M minus chi, we saw if gamma equal to 1. That is ideal. Gamma equal to 0 with freshly cleaved surfaces. Gamma equal to 0 means actually, it will be independent of 5 M. Freshly cleaved surfaces, we saw that 5 B N is constant independent of work function. And you can immediately correlate that in a freshly cleaved surface, the surface state density or interface state density is very high. So, you could guess that the entire deviation from the ideality is due to the presence of surface states, which we did not take into account in ideal theory. Gamma is, when it is between 0 and 1, that is a chemically prepared surface, you get some variation with 5 M, but not as much as 5 M chi. Now, let us take a look at what happens there. So, evidently, because you get in a freshly cleaved surface, gamma equal to 0 or 5 B N independent of the work function indicates that it is due to the surface state or interface state density. Surface is never ideal, and as the density of states, which we call the present by D I T per centimeter square per electron volt due to the dangling bonds at the on surface. Also, there is always a very thin layer of native oxide or some adsorbed layer, mostly native oxide between the metal and the semiconductor surface. So, if you take a freshly cleaved surface or a semiconductor surface and put a metal, it is not directly in contact with the silicon. It is, there is some small gap between them, which is a native oxide or some adsorbed layer, and that we call it as delta, may be nanometer or fraction of a nanometer of that order. So, D I T and delta T values determine gamma. So, deviations from the idealities, some thin layer presence and interface state density, those two are responsible for giving rise to the gamma. Ideally, delta is 0 D I T equal to 0, you will get gamma equal to 1 and you get 5 minus chi. This we have seen in details. I do not have to go through it. So, to recap, remember what you discussed, if you take surface of the semiconductor, there are lot high density of interface states, unless it is passivated and they are all donors below a neutral level E naught, above that they are acceptors. If the Fermi level coincides with the E naught due to the doping in the bulk, if the Fermi level coincides with the E naught, all the charges donor levels are occupied that is neutral, all the acceptor levels are not occupied that is neutral. That is we called that as neutral level. And usually we represent the distance between the energy gap between the E naught and balance banded phi naught. That is the phi naught, which was coming in that expression. E naught is neutral level, E naught minus E V is phi naught. If E f is equal to E naught, that charge on the surface is 0, surface is neutral. That is what we have done. Now, in the n-type semiconductor, Fermi level is there. So, all the levels below this Fermi level between E f and E naught are occupied by electrons. They are negative. They are acceptor levels. Above the neutral level, they are acceptors. When electron occupies that, it is negatively charged. And those negative charges have been taken from the bulk of the semiconductor. As a result, it is depleted. So, the actual diagram will not be like this. That will be like that. We have seen that because the electrons in the surface have been donated from this depletion layer. So, here you can see even if you do not put the metal there, the electron transfer has taken place and Fermi level is getting closer and closer to this neutral level E naught. And the charge in the interface here for a free surface is equal to Q into d I t, where d I t is per centimeter square per electron volt. So, the number of acceptors present between E f and E naught are E f minus E naught into d I t. So, charge is negative there, which is minus Q d I t into E f minus E naught. So, that charge has come from this depletion layer. So, Q I t in magnitude is equal to the Q d in the depletion layer, which is Q N d into W, W is the depletion layer. So, you can see that Fermi level moves closer to neutral level E naught. Supposing the d I t is tending to infinity, infinite with a very small gap between the E f and E naught, you will get the required charges for the depletion layer. It can never coincide with the E naught, but it will get closer and closer. If d I t is tending to very large value, E f minus E naught tends to 0. In the sense Fermi level moves closer and closer to this E naught. So, you say if d I t is very, very large, the Fermi level gets pinned to the E naught level. That is called Fermi level pinning. So, if Fermi level is pinning, you can see that this is coincident with that and the gap between the top layer and this Fermi level, that is of I p n, when I put a metal. So, now, that particular formula that we have put there, this one has been derived way back in 1960s. Still holds good. Cowley and Zey, they have derived that equation for that using the assumption that the derivation just quickly run through that. The assumption is that there is always a thin layer delta and there is always a density of interfaced d I t across the band gap. So, this is that may be assuming that it is oxide, this is the band gap of the conduction band of the oxide, balance band of the oxide and this is the silicon. You can see that there is band bending here and ultimately in thermal equilibrium there is, Fermi level is flat like this between the metal and the semiconductor, it is n time. So, let us see what happened. This is the Fermi level and there is a vacuum level, that is phi m. Now, this layer is very thin. So, if the electrons have energy above this they can tunnel through that, 1 nanometer or less. So, this is still the phi b n, where the conduction band is coming into this point. There are large density of states available here. Electrons you can cut across into this, they can cross. Similarly, electrons can cross from here to here. When we discussed Schottky-Bear theory, we said there is 0 there and it was just a barrier of state available there. Now, on this side of the semiconductor, there is a depletion layer which has a charge q d and in the interface there is a charge between the Fermi level and the neutral level accept us. So, that is q i t. This band diagram I have drawn like this because if I assume that plus charges are there, minus charges are there, there is a voltage drop plus to minus there. This can be corrected by the noting the charge afterwards. So, there is a electric field in this direction from plus to minus here and there is a voltage drop equal to V i. What is the voltage drop across the oxide usually? Whatever charge is there beyond the oxide surface divided by C oxide. In this case, I call it as C i, C interface. So, you have got the voltage drop equal to q d, there is a depletion charge per centimeter square plus q i t whatever charge is present in this red mark that I have shown between the Fermi level and D naught. So, q d plus q i t divided by C i is the voltage drop across the oxide. This may be a small drop, but that affects your bare head phi B n. See when this layer was not there, we said phi B n is equal to phi m minus chi. Now, it is phi m minus V i minus chi. So, instead of phi m minus chi, you have got a term V i which is the drop across oxide. So, phi B n is that quantity. So, all that we have to calculate is what is V i, voltage drop across oxide that is this, q d plus q i t plus V i. q d is positive here, q i t is actually negative. So, if it is negative it may go even that way. If q d is not there or if total charge is negative, the voltage drop will be plus instead of plus here minus here it may go other way. Drop will be rising from that direction. So, now I have taken this whole thing is positive, then I put it in this mark to like this. So, I have written this V i. What is V i now? q d of course, once you know what is the surface potential, you know what is the replace layer width is, what is the charge is. But when that interface state density is very high, it will be this term which will be dominating compared to that. Let us see q i t is this quantity, q d i t, where d i t is interface state density into E f minus E naught. What is E f minus E naught? Take a look at this band gap. I have assigned this quantity as phi b n and this quantity below this E naught is equal to up to this point is phi naught. E naught below E naught to that band that is phi naught and that quantity is phi b n. So, we have got this E g minus phi b n minus phi naught is E f minus E naught. So, in the total band gap here, I subtract this quantity and that quantity and that with this quantity. So, the charge in that gap is equal to q d i t into E f minus E naught. I am putting it as negative because they are acceptors. So, that is why I put it as negative. So, if I do not have q d, if that is negative, the drop will be minus here and plus here. So, field will be in the opposite direction up upward. So, that is taken care of by the sign. So, that substitute for this v i as minus q d i t E f minus E naught by c i. So, what we are looking at is what is phi b n now? phi b n is phi m minus chi minus v i, what we have written there and v i is q d plus q i t by c i and q i t minus is q d i t E f minus E naught that is q d i t E g minus this is what we have just now seen. This is what we have just now seen q i t is band gap minus phi naught minus phi b n here, band gap minus phi naught minus phi b n that is what is left out is E f minus E naught. So, q d is charge per centimeter square in depleted regions, phase charge layer, positive and n-tap silicon, c i is capacitance of the interface layer where per centimeter square epsilon r epsilon 0 by delta standard. So, let us go back and see the phi b n. So, phi b n is phi m minus chi plus v i, this whole thing is v i that is because this is plus q d i that is minus q d i by c i, this whole thing is minus. So, this minus stays with that plus charge, this charge is negative. So, that becomes plus. So, q d i t by c i 2 is what we have just now written, this is a v i due to d i t, due to q i t this is that quantity. So, q i t is the quantity q i t by c i is that quantity. Now, I will not go through that thing, you can actually work it out yourselves. This rearranging the whole thing, you can see there is phi b n here, phi b n here. Take them to the left hand side and right side, I can write it as phi b n is equal to phi b n onto that side, you will have phi b n into 1 plus q d i t by c i going to left hand side. So, you will have phi b n is equal to gamma times phi minus chi, where gamma is actually 1 by 1 plus q d i t by that. So, that is by rearranging that, all that I do is take this on to that side. So, you got phi b n into 1 plus phi q 1 plus q d i t by d c. So, let us not worry about that. So, you get rearranging with gamma phi minus chi, 1 minus gamma e g minus phi b n has gone that side. So, the e g minus phi naught is there and this term is there, that is that gamma term comes into this particular quantity, because gamma is this quantity. When you take it out there, you are dividing right through by 1 plus q d i t by that quantity, it is gamma. So, now you can see if gamma equal to 0, when gamma be equal to 0, d i t is very large. When d i t is very large, infinity finite gamma will be equal to 0. So, gamma equal to 0 means, this term is equal to 1 and this is equal to 0, that is equal to 0. So, when the d i t is very very large, phi b n is equal to e g minus phi naught, independent of i m because gamma equal to 1. That falls with that supports the equation that we have written there, that is this gamma is related to delta and d i t. C i is that is one. So, it depends upon delta and d i t. If delta is 0, of course, you would not get anything. Gamma equal to 0, when d i t equal to infinite and phi b n is e g minus phi naught. This is called Bardin's limit of phi b n. This is independent of phi m. Why do you call Bardin's limit? The surface states were proposed by Bardin, who is one of the Nobel laureates who invented the transistor, bipolar transistor. In fact, the MOSFET did not work as expected. He proposed the theory of surface states, interface states and explained the whole thing and that is why those surface state theory is called Bardin's theory of surface states. This is limit is called the Bardin's limit, i d i t phi b n is e g minus phi naught. Gamma equal to 1, d i t equal to 0 or delta equal to 0, ideal phi minus chi. That is called Schottky limit. Schottky and Bithay, they give the theory of this Schottky diode and a barrier saying that phi minus chi is the barrier. So, ideally Schottky limit on the extreme and Bardin's limit. Now, you can see if it is ideal then you can vary the phi m but it does not happen. But in the worst case, phi b n is equal to e g minus phi naught. So, what is the result of that? In silicon, phi naught is 1 third, phi naught is e g by 3. So, what will be the phi b n in silicon? For most of the semiconductors, it will be minus e g by 3. That is 2 thirds of e g. So, 1.1 is the band gap. So, you will have the barrier hit over 0.7, 0.7 pi, electron volts. It will always be rectifying because the barrier is high. If the barrier hit is low, you would have got omicontact. So, if you get rectifying in the case of n type material, if you make in the p type again thermal opening will be there. What will be the barrier hit phi b p? Supposing this is 2 thirds of e g for the p type material, barrier hit for holes will be e g minus that. See, that is 2 thirds. That is barrier hit for electrons. This is barrier hit for holes. So, if this is 2 thirds e g, that is 1 third e g. So, barrier hit for holes will be smaller. So, it will be easier to make p-channel devices with metal semiconductor to contact because it makes omicontact on to the holes or p-channel. So, this is what we showed for germanium. The germanium we see, the barrier hit for electrons was something like that. 0.66 is the band gap and it was very close to the band gap there. When the phi m is varied, very little change in the barrier hit. So, in germanium it is a hopeless situation to make a n-channel MOSFET because it will form a barrier hit is equal to very close to the band gap. Band gap is 0.66, phi naught is 0.09. So, very close to 0.6 electron volts. So, it will be very bad situation to make n-channel device, but anything you deposit on germanium will make omicontact because barrier hit is very small for holes. So, it will be very easy to make p-channel MOSFETs with metal semiconductor to contact with germanium. That is good news for people who want to make germanium p-channel MOSFETs. So, if you want to get n-channel MOSFET with germanium or silicon, you have got to do something else. So, let us just see what are the situation there. So, this is the Fermi level between which I was talking of in the case of gallium arsenide etcetera, it is two-thirds of V G, pi b n. In the case of germanium, phi naught is 0.09. Therefore, phi b n is about 0.57. So, rectifying always you put a metal on these semiconductors, it will make rectifying contact. So, it is very easy to make Schottky barrier diodes on n-type materials and it is very difficult to make omicontact like that. So, effect of Fermi level pinning, almost all metals form rectifying contact on n-type silicon and gallium arsenide and also on germanium. They form lower barrier hit contacts that is omicontact on p-type silicon and p-type gallium arsenide. Therefore, it is easier to realize two-channel Schottky barrier source strain MOSFETs than n-channel Schottky barrier source strain MOSFETs on silicon and gallium arsenide in germanium, because n-channel will make it a high barrier hit. So, number of electrons which are available for supplying to the channel will be limited by this if you recall go back to this one if you see. See if this barrier hit is high here, number of electrons which are available to cross the barrier are reduced less that is the problem. So, normally when you put a metal it becomes rectifying unless you take care of do something to the surface to unpin that Fermi level. Now, let us quickly go through some of the things that are there like the p-channel Schottky barrier. The first of those you know way back this was done by J and Kuanake, platinum silicide, metal semiconductor contact at the source. This is not the endless or so much. So, once you see that you can make easily omicontact on to the p-channel materials if it is a p-type materials, if it is a p-channel transistor, platinum silicide can make omicontact on to that that is low barrier rate for holes. So, people thought of making let us see p-channel Schottky barrier source strain MOSFETs on silicon. They made that same approach, gate oxide about 25 nanometers. We are talking of 1981. So, gate oxide 25 nanometer and phosphorous gate as shown in the metal, but it is phosphorous looped polysilicon gate they have used that and then what they did was they transit a bit of W and channel length was L 1 micron to 10 micron various lengths. Long channel we have seen in for L equal to 1 micron. So, n-type silicon 10 to the power of 15. Just go through quickly, phosphorous looped gate polysilicon was deposited pattern and its sites were protected by deposited SI vote. First the gate was decided, sites were protected. SI vote was removed from source and drain regions where you want to put this contact SI vote was removed approximately about 15 nanometer of platinum was buttered and then sintered at 625 degree centigrade for 30 minutes in argon to form platinum silicide. In fact, it consumes silicon that is why it is shown here as getting inside into silicon. It consumes silicon and you get about 30 nanometers of platinum silicide over all the previously deposited silicon region. Wherever it is a sports you get that platinum silicide. Other places there is no silicon there is no platinum silicide. So, what you do is the unreacted platinum was removed by aqueorizer or you can use some reactive plus matching. 5 B P the nice thing about that is 5 B P is very low with the holes or this P channel that is barrel height is low that is about 0.24 electron volt. It is close to the formula of pinning type. So, that means actually you can make transistors working transistors because barrel height for holes is very very small. There is supply of holes is very much. Now, let us just quickly take a look at the energy band diagram if you like. There is n type silicon, there is platinum silicide contact here, there is a depletion layer here. So, n type is no beta oxide or no voltage applied to the gate. There is a depletion layer, there is n type region, there is a conduction band, there is a balance band. This is to show the balance band. Now, when I have a metal oxide over that and if I apply a plus voltage to that the surface and the surface if you take the energy band diagram that will be inverted. N has become P. This is very interesting diagram. Please take a look at that. There it was like that. I have not applied any drain voltage. Still it is thermal equilibrium situation there. So, that is the permeable. And here this metal semiconductor contact, there will be depletion layer here just in this point P and this is metal and P channel. It is like a metal and P type semiconductor. It is equivalent of that. So, there will be depletion layer there, small layer will be there. There is a diode. It is a P channel with the metal semiconductor to contact P and metal and P all what equivalent of that. You have got a slightly depletion layer. This is the energy band diagram. Now, if I apply voltage to the drain, the P channel device I want to collect the holes negative voltage to the drain. If I apply a negative voltage to the drain, I am looking this energy band diagram is not in the bulk. It is here on the top. Here it is still n type. So, on the top only I am drawing the diagram. So, what happens to the diagram? Minus here plus here. So, across this shaded region is actually the inverted P layer. There is a drop plus to minus. If there is plus to minus here, there is a small depleted layer there. There is a NP diode. Energy band diagram bends. You know, it is more difficult to take electrons from plus to minus. That means the energy band diagram will be higher on this side. So, it bends upward from the left hand side to the right hand side. So, the indication is minus there and plus here. Now, whatever holes which are injected, bang and go through this. How much it is collected here depends upon how much is the voltage across the channel. And if this is small, that can supply that. If this barrier head is large, it cannot supply that. Current supply will be limited. That is why this sort of device has worked. But what they say saw was the output current in the Schottky barrier MOSFETs were found to be smaller than those for conventional MOSFET. If these were P plus region, you would have got more current than that. The whole thing is because from part of the applied voltage goes into this part. See, this diode, if you recall, I do not know whether you are able to recall that. When I have no bias across that, the hole injection from here and here will be canceling each other. If I have net hole injection from here to here, I must reduce the barrier. I must reverse bias that. That is minus here plus here. So, part of the applied voltage will go to this junction plus minus here. So, that this barrier is increased. This is brought down there. So, when you have a, I do not know whether you remember. See, if you go to this one, N type if you take. See, if I do not have some drop here, across this layer there, here it is plus and minus. The electron injected from here and here is the same thing. I must have a plus voltage here so that this is metal N type region is reverse biased. So, that this is brought down a bit. So, electrons cannot be injected from here to here. Only these electrons are injected backward. Same argument holds good for the case of p channel device. Instead of plus minus, it is minus plus. So, part of the applied voltage will go into this junction. So, the full thing is not available for that, for a current transport. So, now, so you get equivalently you can put this as, in this, this is the inverted diagram. This is before inversion. This is after inversion. The whole injection from here to here is possible if there is some reduction of the barrier on this side. So, this portion you are putting it as a diode. In fact, what happens is the applied voltage minus here is appearing across some part of it goes into this region. Minus here and plus here means it is reverse biased. The diode when it is reverse, see the most important concept in Schottky Barrier is it can in the, if it is a N type material, it can inject electrons from the metal to semiconductor if it is reverse biased. When it is forward biased, it injects electrons from the semiconductor to the metal. The p channel device it can inject holes from the semiconductor to the metal if it is reverse biased. If it is forward biased, it can inject holes from semiconductor to the metal. So, this will be reverse biased condition minus plus. So, applied voltage will get shared between this and this. So, part of the voltage goes there. More and more voltage gets tripped, but more and more carriers can be injected across a barrier. So, I think that is you bring one of the barriers. This barrier is not changing. Only this barrier you can reduce. That is you can bring it down so that the carry electrons which are distributed above that their level is brought down. There is no injection from the right to the left, but this barrier is not changing. So, there will be an injection of carrier from here either holes or electrons. So, in either way a reverse biased voltage would appear across and it comes from the drain itself. So, part of the voltage will go to that. So, current available for conduction will be reduced or to put it in the more emphatic way, but number of holes available here is depends upon how much lower the barrier is. Less the barrier, more holes are available. So, the current in these cases was observed to be lower than what it is. So, the key thing in these devices is to reduce the barrier height. They be channel. Now, let us see whether people have tried to do something about the n channel devices. So, what they did here, they fabricated n channel devices. They used a tantalum, pi b n is pi b p is 0.7 electron volts. The pi b p is large there, pi b n is small there. So, they were hoping that they can just have some some sort of short key barrier. So, they made it is the same way they have done the thing. You can see that the n channel short key barrier MOSFET structure T oxide 90 nanometer, L 10 micrometers. They are not to be they do not worry about short nanometers etcetera. 100 nanometer thick tantalum ion beam deposited on and sintered at 450 for 30 minutes in forming gas defined by etching in the two defined this portion. After forming this gate region polysilicon exactly same way before you open a contact tantalum sputtered, annealed in forming gas that forming at the annealing has slightly passivated those interface states. So, because of that they could get some sort of MOSFET action. So, that is what. So, you can see now when you invert it and if I apply plus voltage to drain that is energy band diagram conduction band balance band. I hope you understand this. In the previous case you had the band diagram going up there because plus to minus here it is minus to plus. Tain is plus then channel device. So, same problem they had ideally if you can get the MOSFET characteristic like this. They got you know same equivalent circuit the MOSFET with the diode which is the source channel diode. In the previous case it was P 2 metal in that case it is metal to N. Diode is reversed that is the diode. Now, you can even have a plus voltage plus minus plus minus this is reversed biased. When it is reversed biased it enables electron to be injected from the source to the channel. But for the electron to be injected from source to the channel there must be a reverse bias across that that comes from this applied voltage. So, part of the applied voltage goes into this diode. That is why in the ideal MOSFET you may get the characteristic like that. But ideal means the source and drain diffused the metal semiconductor contact the there is a for the same current you have to go apply higher voltage because part of the voltage has gone to this V s that is V d minus V s is the one. So, you can use same equation that used for the MOSFET. So, they did get MOSFET action but lower currents or you apply more drain voltage for that. This is the barrier between the source and this channel is the thing that they observed. Now, you can write the equations I d. So, you can see the drain current you can write in terms of the potential drop across a channel. What is the potential drop across a channel? V d s minus that V f s source is not 0. So, part of it has gone to that. So, V d s minus. So, in the linear region you get V c oxide of the well same MOSFET equation into V g minus V threshold into V d s you write. But V d s in this case V d minus V f s V d minus V f s V f s is the V threshold that is the Schottky diode which is between the channel and the metal minus V d s square by 2 but V d s c V d minus V f s. So, you can see this entire thing is smaller than what you usually see for a given V d and just notice this is the current which is collected by this voltage across the channel V d minus V f s. So, whatever current is flowing through a channel is supplied by the source. What is the current supplied by the source? The reverse bias current of the diode, correct? Because across the barrier. So, that is why the reverse bias voltage keeps on increasing as you increase that and it supplies more and more current. But at each point whatever is the V f s is the reverse bias voltage across the diode. What is the reverse current across the diode? A star t square this quantity into 1 minus this quantity. When V f s is very very large that goes down to 0 and you get the I naught. So, maximum that you can get is I naught of the diode. So, I naught of the diode will be unlimited if it is ohmic. If the barrier is very small you can have large I naught. So, whether it is controlled by this short circuit or reverse current or by this MOSFET action depends upon the barrier height. So, lower barrier height is a key thing for this entire MOSFET thing. So, just let me quickly go through some other things that latest things which are there before I wind up this thing. So, they have tried varieties of materials. We have desperation on this thing because to get down through this because it has several advantages. Silicides of other materials for N-channels or key source transistors have been tried. For P-channel devices platinum silicide is very good. Payback 1981 itself demonstrated that gives 0.24 to 0.28 5 Bp for P-channel devices. You get I on off about 1048. So, P-channel devices in the case of silicon is no problem. From the same token what about P-channel devices in the case of germanium? What will you say? What is the barrier height there? Here is 0.24 when the Fermi level pinning is there in the case of P-channel device or P-type substrate it is 0.09 is barrier height very very small. So, excellent ohmic contact you can get for germanium excellent P-channel MOSFETs can be made with germanium. That means very good news for germanium people because germanium has got hole mobility much larger than that of hole mobility in silicon. So, you can think of germanium P-channel MOSFETs, but then if you get low barrier height for holes on the same token you will say that barrier height for electrons is high. Very difficult to make any channel devices. We will get down to those things either in this lecture or when you go to germanium devices. So, here silicon was the desperation. They have to FBM metal which has I m of that quantity they got fairly good ion of ratios. Iterbium gave much smaller barrier height. So, Iterbium was the one that they advocated for n-channel P-channel MOSFET P-channel platinum philicide Iterbium philicide. So, those are the things which they have tried out and Iterbium gave about 5 Bn of about 0.27 some sort of accepted devices they were fabricated there. Of course, they had to make some passivation using the forming gas annealing etcetera, but not enough you have to get better. So, in summary of these about these things quickly go through because a few more things we discussed the metal cement source drain are inherently lower resistance. You know these are all we have discussed already lower resistance you can get in use metal source drain, metal source injunctions to this channel from Schottky barrier. It forms all this Schottky barrier injunctions eliminate parasitic BJT. We already discussed that I am not this is not summary of my talk, but again advertisement for this Schottky barrier devices. Also low thermal budget to make the metal contact on to the source drain. You do not have to have high temperature diffusion and if it is low temperature Schottky it is excellent to make high k dielectric that is why people are looking at metal cement dielectric source drain. High k dielectric when you put you may realize the gate etcetera you can even go for metal gate then afterwards source drain you do not want to do diffusion. You want to do it at low temperature you can use that metal cement dielectric contact. So, that is why people are looking more and more into that nano scale devices. Together these features and benefits make Schottky barrier CMOS technology and attractive candidate for scaling to sub nanometer below 25 nanometer coupled with SO approach promises down to 10 nanometer. Now present status I just have some more things from 2004 right up to recent ones. Considerable advancement has taken place in Schottky barrier MOS theory for the past decade. Platinum scale side source drain devices with 25 nanometer all those things have been demonstrated mainly for p channel. The on current and off current of these devices does not admit the requirements requirements. Even though Schottky barrier CMOS specs with 280 gigahertz 30 nanometer gate lengths have been fabricated even earlier 2004 p channel devices have been fabricated highest for any MOSFET because of that low resistance etcetera p channel not n channel yttrium aterbium not yttrium aterbium silicide has been identified as an alternative to other materials because barrier heat is low. So, that is one of the things people have been looking at to some degree of success. Now there is a small h you may be able to make n channel MOSFETs with the aterbium with 0.27 phi bn, but if you use the same approach for p channel device phi bp is large because phi bn if it is small phi bp is large because you know that phi bn plus plus phi bp cg. So, you will end up with large barrier heat for the p channel. So, if you want to make CMOS you must have the ability to overcome this problem not by adjusting the work function you must have the ability to have both phi bp under control and phi bn under control. So, if I am using platinum silicide as contact I can make p channel MOSFET without any difficulty because barrier heat is very small 0.24 electron volt even in germanium I can make it very small because it is very very small not 9 per minute. So, the Schottky barrier heat phi b of platinum silicide contacts on n type silicon was you can tune that if you can tune that barrier heat by sulphur using sulphur as a pass event or implanting sulphur you are in business because you let us see how this is done the contacts on n type silicon was tuned by sulphur segregation at the platinum silicide silicon interface. Platinum silicide contacts were found by rapid thermal annealing at 450 degree centigrade for 30 seconds in nitrogen bed. So, what is done is taken types of state to study this if you want to make n channel you have to take p type and implant sulphur. Sulphur was implanted to prior to platinum deposition first implant sulphur and segregated at the interface during platinum silicide forming implant sulphur deposit platinum anneal at 450 degree centigrade rapid thermal annealing what is rapid thermal annealing take temperature very quickly spike 30 seconds bring it down. If you keep long enough in at 450 degree centigrade the sulphur may come out now what happens it is just segregates into interface. Platinum silicide is formed it is just segregating segregating means it is getting cluster of sulphur at the platinum silicide silicon surface. It was observed that barrier heat could be tuned by changing the sulphur dose a minimum barrier heat up to 0.12 electron volts was observed on n type from 0.00 silicon surface that is very good news. See if you do not implant you get a barrier heat of so how much 1.1 minus 0.24. So, about 0.8 or so 0.8 to 6 or so barrier heat, but on p type you get 0.24 or 0.2 to 0.24 electron volts low barrier heat on n type I can adjust the dose and get low barrier heat. That means I can make n channel devices on that. Since platinum silicide naturally provides a small 5 B P, this 5 B has complained 5 B of 0.2 electron volts on p type silicon it carries the potential to serve as single metal force drain contact metal on C-mose integrated circuits. I hope you understand that same platinum can be used in the regions where you want to make p channel MOSFET do not implant sulphur. You get a barrier heat which is 5 B P low for the p channel 0.2 electron volts. In the region where you want to make n channel devices you implant sulphur. You can control that barrier heat by controlling the dose of sulphur. So, you can make low barrier heat for n channel. So, what happens there? Why this sort of thing? You are moving the changing the location of that thinning. So, this is one of those papers which appeared in 2009. N channel silky barrier source drain MOSFET, sulphur implantation and silicide formation for n channel devices. Tuning of platinum silicide short key barrier height on n silicon by sulphur segregation. So, sulphur implantation dose per centimeter square 2 into 10 to the power 13, 4, 6, 8, 10, 10 to the power 14 per centimeter square. Barrier heat originally is 0.8 if you do not implant. If you take entire material and make platinum silicide it is about 0.8. But for different doses the barrier heat is reduced even very small we can reduce that. What they have observed is sulphur is known to create donor like deep trap level near the conduction band of silicon. See this is actually what I have shown as a density a clustered region of sulphur donor levels here. See if you take usually what you do is you have the energy band diagram like that conduction band, finance band. You have the neutral level here. You have all these are donors. All these are acceptors. The permeable always tends to get pinned to the neutral level to balance everything. So, that is why permeable goes here in this portion. That is the EF gets to pinned to that. But now in this case what you are doing is your what you do is you have this energy band diagram like this. You have large density of sulphur which are donors there. So, you have got originally you had all donors here and all acceptors there. Now there is a large density of donors here much more larger than that 10 to the power 14 etcetera you are implanting. So, permeable gets pinned down to this portion. How much this is actually not like that in fact it will be distributed like this donor levels. So, permeable gets pinned down to this portion where density of donors are very large even compensating all these things. It is equivalent of saying you have got donor levels here the acceptors here and donor levels here. So, permeable will go into that portion. Let me put it down again put it more clearly that is the conduction band that is the balance band. Then you have got donors large density of donors here they are acceptors. So, you can say that neutral level is actually somewhere here there is much more than this donor which are there present. So, your permeable actually gets pinned down to this point that is how much it is there depends upon how much sulphur implanting more implant the spreads more and this move up here see from the Heisenberg theory or the no two levels can exist simultaneously if you more implant more sulphur more number of trap levels they cannot exist in the same place it will spread out. So, it moves up there and you got the permeable closer and closer to conduction band. So, you are able to reduce this there ahead by putting more and more of those more and more of those I think I should take this off more and more of those sulphur atoms. So, this is the I V characteristics of those Schottky barrier diodes see when I without sulphur this is love scale please remember 10 to the power of minus 6 ampere per centimeter square that is the forward characteristics. Sulfur at 10 to the power of 13 reverse current has increased forward also has increased pi 10 to the power of 13 reverse current this is 0 love scale large reverse current large forward current front of 14 very close to home contact. So, the home contact is this matrix on love scale in the linear scale it is like that this is what will happen in this case. So, what I am trying to point out here is the sulphur passivation has been the key thing people have been trying out. In fact, even in germany it can be tried out. So, lot of references are there which have come over the years 84 and all 2004. In fact, some work has been done here also on sulphur passivation. One of our MS students Arun, my cell plant was no convert, formal level deep inning at the germanium Schottky interface through sulphur passivation. That was not implantation that was by chemical treatment. In fact, in gallium arsenide also the pinning deep inning has been illustrated by using the sulphur passivation. So, when I discuss about the germanium we will discuss that in some more details. Of course, we can go through some one paper for Schottky barrier this book also you can see and you can will this paper which has come in 2010 you can see. So, that we will conclude our discussion on Schottky source chain contacts. We will take on germanium go to new materials with classical and non classical structures we will discuss in next lecture onwards.