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Published on Nov 23, 2016
PISCES: A P4-Enabled Open vSwitch- Muhammad Shahbaz, Princeton University and Cian Ferriter, Intel
Hypervisors use software switches to steer packets to and from virtual machines (VMs). These switches frequently need upgrading and customization---to support new protocol headers or encapsulations for tunneling and overlays, to improve measurement and debugging features, and even to add middlebox-like functions. Software switches are typically based on a large body of code, including kernel code, and changing the switch is a formidable undertaking requiring domain mastery of network protocol design and developing, testing, and maintaining a large, complex codebase. Changing how a software switch forwards packets should not require intimate knowledge of its implementation. Instead, it should be possible to specify how packets are processed and forwarded in a high-level domain-specific language (DSL) such as P4, and compiled to run on a software switch. We present PISCES, a software switch derived from Open vSwitch (OVS) DPDK-based implementation, a hard-wired hypervisor switch, whose behavior is customized using P4. PISCES is not hard-wired to specific protocols; this independence makes it easy to add new features. We also show how the compiler can analyze the high-level specification to optimize forwarding performance. Our evaluation shows that PISCES performs comparably to native OVS's DPDK-based implementation and that PISCES programs are about 40 times shorter than equivalent changes to OVS source code.
About Cian Ferriter Cian Ferriter is a Software Engineer at Intel, Ireland. His current work focuses on adding support for P4 in OVS. Specifically, he is working on building a programmable micro-flow cache, configured via P4.
About Muhammad Shahbaz Muhammad Shahbaz is a third year Ph.D. student in the Department of Computer Science at Princeton University. His research focuses on the application of software-defined networking (SDN) in campus, enterprise and wide-area networks, network measurement and testing, and language abstractions for programmable data planes. Previously, he worked as a research assistant at the University of Cambridge, Computer Laboratory on the CTSRD and MRC2 projects and was a core member of the NetFPGA-10G project initiated by Stanford University. He received his Bachelor's degree from the Department of Computer Engineering at National University of Sciences and Technology.