 Hello and welcome to this presentation of the STM32G4 power controller. The STM32G4's power management functions and all low power modes will also be covered in this presentation. STM32G4 devices feature a flexible power control which increases flexibility in power mode management and further reduces the overall application consumption. This slide details the consumption in the various power modes for the STM32G4-74. Run mode can support a system clock running at up to 170 MHz with only 173 microamps per MHz. At 26 MHz the consumption is even lower, 128 microamps per MHz. STM32G4 devices support 7 main low power modes. Low power run, sleep, low power sleep, stop 0, stop 1, standby and shutdown modes. Each mode can be configured in many ways, providing several additional sub modes. In addition, STM32G4 devices support a battery backup domain called VBAT. The high flexibility in power management provides both high performance with a core mark score equal of 3.42 MHz together with an outstanding power efficiency. The STM32G4 has several key features related to power management. Several low power modes down to 130 nanoamps while it is still possible to wake up the MCU with an event on an I.O. For only 435 nanoamps, 16 kilobytes of SRAM can be retained assuming a 1.8 volt VDD power supply. A large number of peripherals can wake up from the various low power modes. Dynamic consumption is down to 128 microamps per MHz, executing from flash memory. A battery backup domain called VBAT includes the RTC and the backup registers. Several power supplies are independent, enabling the reduction of the MCU power consumption while some peripherals are supplied at higher voltages. Thanks to the large number of power modes, STM32G4 devices offer high flexibility to minimize the power consumption and adjust it depending on active peripherals, required performance and needed wake-up sources. STM32G4 devices have several independent power supplies which can be set at different voltages or tied together. The main power supply is VDD, supplying almost all IOs except those part of the VBAT domain. VDD also supplies the flash memory, the reset block, temperature sensor and all internal clock sources. In addition, it supplies the standby circuitry, which includes the wake-up logic and independent watchdog. VDD supplies voltage regulators, which provide the V-Core supply. V-Core supplies most of the digital peripherals, SRAMs and flash memory controller. VDDA voltage supplies the analog peripherals. The Vref plus pin provides the reference voltage to the analog to digital and to digital to analog converters. It is also the output of the internal voltage reference buffer when enabled. A backup battery can be connected to VBAT pin to supply the backup domain. The main power supply, VDD, ensures full feature operation in all power modes from 1.71 up to 3.6V, enabling it to be supplied by an external 1.8V regulator. Device functionality is guaranteed down to 1.6V, the minimum voltage after which a power-down reset is generated. Other independent supplies are provided to enable peripherals to operate at a different voltage. VDDA is the external analog power supply for analog to digital converters. Digital to analog converters, voltage reference buffer, operational amplifiers and comparators. When the analog to digital converters or comparators are used, the VDDA voltage must be greater than 1.62V. When the digital to analog converters are used, VDDA must be greater than 1.71V. When the operational amplifiers are used, VDDA must be greater than 2.0V. When the voltage reference buffer is used, VDDA must be greater than 2.4V. A backup domain is supplied by VBAT, which must be greater than 1.55V. The backup domain contains the RTC, the 32.768 kHz LSE external oscillator and the tamp block containing the 128-byte backup registers. The ADC and DAC voltage references can be provided either by an external supply voltage or by the internal reference buffer. This improves the performance of the converters by providing an isolated and independent reference voltage. The VREF plus pin and thus the internal voltage reference is not available on 32-pin packages. In those packages, the VREF plus pin is double bonded with VDDA and the internal voltage buffer must be kept disabled. The voltage reference can be provided through the VDDA pin in those packages. LQFP128 package has two VREF plus pins. The power supply supervisor guarantees a safe and ultra-low power reset management. STM32G4 devices embed a power-on reset, or POR, and a power-down reset, or PDR, which are always enabled in all power modes except shutdown mode. The brown-out reset, or POR, ensures reset generation as soon as the MCU power supply drops below the selected threshold, regardless of the VDD slope. Four thresholds from 1.7 to 2.8 volt can be selected by option byte programmed in flash memory. A power voltage detector, or PVD, can generate an interrupt when VDD crosses the selected threshold. The PVD can be enabled in all modes except standby and shutdown modes. The threshold is selected by software among seven possible values. In addition, comparisons can be done between VREF-INT and the PVD-IN external pin. The VDDA power supply can be independent from VDD and can be monitored with two peripheral voltage monitoring, or PVM. The power resets POR and POR reset all registers except those in the backup domain powered by VBAT, which contains the RTC and TAMP blocks and the external low-speed oscillator LSE. When exiting standby mode, all registers powered by the main regulator are reset. When exiting shutdown mode, a power reset is generated. Five bore levels can be selected through option bytes. During power on, the bore keeps the device under reset until the supply voltage VDD reaches the specified VBOR-X threshold. When VDD drops below the selected threshold, a device reset is generated. When VDD is above the VBOR-X upper limit, the device reset is released and the system can start. Two embedded linear voltage regulators supply all the digital circuitries except for the standby circuitry and the backup domain. The regulator output voltage, VCOR, can be programmed by software to two different values depending on the performance and the power consumption requirements. This is called dynamic voltage scaling. The figure on the left indicates the VCOR voltage level required according to the frequency. Depending on the application mode, VCOR is provided either by the main voltage regulator for run, sleep and stop, zero modes, or by the low power regulator for low power run, low power sleep, stop one modes. The regulators are off in standby and shutdown mode. When SRAM 2 content is preserved in standby mode, the low power regulator remains on and provides the SRAM 2 supply. In run mode, the CPU is clocked and programmed can be executed from flash or SRAM memory. In range 1, the system clock is up to 170 MHz. In range 2, it is up to 26 MHz. By default, the SRAM clocks are enabled. They can be individually gated off during sleep mode by software. All peripherals can be activated in range 1. In run mode, the voltage scaling range 2 is the medium performance range, enabling a system clock up to 26 MHz. When executing from SRAM, the flash consumption can be saved by configuring the flash in power down mode and by gating its clock off. All peripherals can be activated except the USB device and random number generator. All clocks can be enabled. In low power run mode, the CPU is clocked and programmed can be executed from flash or SRAM. Additionally, the flash can be completely unpowered to save power. The system clock is limited to 2 MHz. The main regulator is switched off and supply to digital blocks is provided by the low power regulator. In low power mode, all peripherals except the USB device and random number generator can be active. The run mode, thanks to voltage scaling and the low power run mode, offer flexibility between required performance and consumption. In run mode, range 1, when boost mode is active, the system clock is limited to 170 MHz and the internal and external oscillators and the PLL can be used. In run mode, range 1, when boost mode is disabled, the system clock is limited to 150 MHz and the internal and external oscillators and the PLL can be used. In run mode, range 2, the system clock is limited to 26 MHz and the internal and external oscillators as well as the PLL can be used but must be limited to 26 MHz. In low power run mode, the system clock must be limited to 2 MHz. Each peripheral clock can be configured to be on or off in run and low power run modes. By default, all peripherals clocks are off except the flash interface clock. The SRAM clock is always on in run mode. When running from SRAM in run or low power run modes, the flash memory can be put in power down mode thanks to software and the flash clock can be switched off. The flash memory must not be accessed when it is switched off. Consequently, interrupt vectors must be mapped in SRAM using the Cortex M4 vector table offset register. The current consumption in run or low power run modes depends on several parameters. First, the executed binary code. That means the program itself plus the compiler impact. Then it depends on the program location in the memory, the device software configuration, the IO pin loading and switching rate and the temperature. The consumption also depends on whether the code is executed from flash memory or from SRAM. Energy efficiency is better when the flash prefetch and the instruction cache are enabled. Executing from flash consumes more than executing from SRAM because the flash memory belongs to the VDD power domain while the SRAM belongs to the Vcore power domain. Sleep and low power sleep modes enable all peripherals to be used and features the fastest wake up time. In these modes, the CPU is stopped and each peripheral clock can be configured by software to be gated on or off during the sleep and low power sleep modes. These modes are entered by executing the assembler instruction, wait for interrupt, WFI, or wait for event, WFE. When executed in low power run mode, the device enters low power sleep mode. Depending on the sleep on exit bit configuration in the Cortex-M4 system controller register, the MCU enters sleep mode as soon as the instruction is executed or as soon as it exits the lowest priority interrupt subroutine. This last configuration saves time and consumption by avoiding the need to pop and push the stack when exiting the low power mode. However, all computations must be done in Cortex-M4 handler mode because the thread mode is no longer used. In sleep mode, the CPU clocks are off. In range 1, the system clock is up to 170 MHz, in range 2 it is up to 26 MHz. By default, the SRAM clocks are enabled. They can be individually gated off during sleep mode by software. All peripherals can be activated in range 1. In sleep mode, range 2, all peripherals can be activated except the USB device and random number generator. In low power sleep mode, the CPU clock is off and the logic is supplied by the low power regulator. The system clock is up to 2 MHz. Flash memory can be configured in power down and can be gated off. SRAMs can be gated off. All peripherals can be activated except the USB, OTG and random number generator. STM32G4 devices features two stop modes, stop 0 and 1, which are the lowest power modes with full retention and only a few microseconds wake up time to run modes at 16 MHz. The contents of SRAM and all peripherals registers are preserved in stop modes. All high speed clocks are stopped. The 32.768 kHz external oscillator and 32 kHz internal oscillator can be enabled. Several peripherals can be active and wake up from stop mode. System clock on wake up is the internal high speed oscillator at 16 MHz. Stop 1 is similar to stop 0 with the main regulator switched off. The voltage regulator is configured in main regulator mode. All clocks in the V-core domain are stopped. The PLL and the HSE oscillators are disabled. The RTC, clocked by the internal or external low speed oscillator, can remain active. The brownout reset is always enabled. Most of the peripheral clocks are gated off. Several peripherals can be functional in stop 0 mode. Power voltage detector, peripheral voltage monitor, digital 2 analog converters, operational amplifiers, comparators, independent watchdog, low power timer, I2C, UART and low power UART and UCPD. The events from all IOs can wake up from stop 0 mode as well as the interrupt generated by the active peripherals. The I2C, UART or LP UART can switch the HSI16 on during the stop mode in order to recognize their wake up condition and switch off the HSI16 after receiving the frame if it is not a wake up frame. In this case, the HSI16 clock is propagated only to the peripheral requesting it. Stop 1 mode is very similar to stop 0 except that the power figures are much lower as the main regulator is stopped and replaced by the low power regulator. Flash memory as well as HSI16 are configurable. They can be stopped or kept enabled. When comparing stop modes, stop 0 mode consumption is higher than stop 1 mode consumption, but the wake up time is shorter. Stop 0 mode keeps the main regulator enabled, enabling a very short wake up time of 3 microseconds when restarting from the RAM to the expense of a higher consumption than stop 1. The I2C address recognition is functional in both stop modes and can generate a wake up event in case of an address match. The UART and LP UART byte reception is functional in both stop modes and can generate a wake up event in case of start detection or byte reception or address match event. When clocked by the internal or external low speed oscillator, the low power timer can wake up the MCU with all its events. The standby mode is the lowest power mode in which the 16 kilobyte of SRAM2 can be retained. The automatic switch from VDD to VBAT is supported and the IOS level can be configured by independent pull up and pull down circuitry. By default, the voltage regulators are in power down mode and the SRAM contents and peripherals registers are lost. The 128 byte backup registers are always retained. The brownout reset is always on to ensure a safe reset regardless of the VDD slope. Each IO can be configured with or without a pull up or pull down, which is applied and released thanks to the APC control bit. This controls the input state of external components even during standby mode. Five wake up pins are available to wake up the device from standby mode. The polarity of each of the five wake up pins is configurable. The wake up clock is HSI with a frequency of 16 MHz. In standby mode with SRAM2 the main regulator is power down and the low power regulator supplies the SRAM to preserve its content. The RTC clocked by the internal or external low speed oscillator may remain active. The brownout reset is always enabled. The independent watchdog can also be enabled in standby mode. Reset brownout reset RTC and tamper detection, independent watchdog and any event on the five wake up pins can exit the microcontroller from standby mode. In standby mode without SRAM retention both main and low power regulators are powered down. Wake up events and available peripherals as well as wake up sources are the same as in standby mode with SRAM. The shutdown mode is the lowest power mode of the STM32G4 with only 15 nanoamps at 1.8 volt. This mode is similar to standby mode but without any power monitoring. The power down reset is disabled and the switch to VBAT is not supported in shutdown mode. Hence the product state is not guaranteed in case the power supply is lowered below 1.6 volt. The LSI is not available and consequently the independent watchdog is also not available. A power reset is generated when the device exits shutdown mode. All registers are reset except those in the backup domain and a reset signal is generated on the pad. The 128 byte backup registers are retained in shutdown mode. The wake up sources are the five wake up pins and the RTC events including tampers. When exiting shutdown mode the wake up clock is HSI at 16 MHz. In shutdown mode the main regulator and the low power regulator are powered down. The RTC clocked by the external low speed oscillator can remain active. The brownout reset is deactivated. Only the external low speed clock can be enabled. The wake up events are the RTC and tamper events, the reset and the five wake up pins. Here you can see the summary of all the STM32G4 power modes. From run mode it is possible to access all power modes except low power sleep mode. In order to enter low power sleep mode it is required to move first to low power run mode and execute a wait for interrupt or wait for event instruction while the regulator is the low power regulator. On the other hand when exiting low power sleep mode the STM32G4 is in low power run mode. When the device is in low power run mode it is possible to transition to all low power modes except sleep and stop zero modes. Stop zero mode can only be entered from run mode. If the device enters stop one mode from low power run mode it will exit in low power run mode. If the device enters standby or shutdown it will exit in run mode. The backup domain keeps the RTC fully functional and preserves the backup registers in case the VDD supply is down thanks to a backup battery connected to the VBAT pin. The backup domain contains the RTC clocked by the low speed external oscillator at 32.768 kHz. Three tamper pins are functional in VBAT mode and will erase the 128 byte backup registers also included in the VBAT domain in case of intrusion detection. The backup domain also contains the RTC clock control logic. In case VDD drops below a certain threshold the backup domain power supply automatically switches to VBAT. When VDD is back to normal the backup domain power supply automatically switches back to VDD. The VBAT voltage is internally connected to an ADC input channel in order to monitor the backup battery level. When VDD is present the battery connected to VBAT can be charged from the VDD supply. The battery charging feature enables the charging of a super cap connected to VBAT pin through internal resistor when VDD supply is present. The charging is enabled by software and is done either through a 5 kilo ohm or 1.5 kilo ohm resistor depending on software. Battery charging is automatically disabled in VBAT mode. VBE bit field of the PWR-CR4 register enables battery charging. VBR-S bit field of the PWR-CR4 register selects the resistance value. During the startup phase if VDD is established in less than TRST tempo and VDD greater than VBAT plus 0.6 volt a current may be injected into VBAT through an internal diode connected between VDD and the power switch VBAT. If the power supply or battery connected to the VBAT pin cannot support this current injection it is strongly recommended to connect an external low drop diode between this power supply and the VBAT pin. In VBAT mode the main regulator and the low power regulator are powered down. The RTC and tamper clocked by the external low speed oscillator can remain active. Only the external low speed clock can be enabled. The only powered block is the backup domain that includes RTC and tamper and the return to normal execution happens once VDD supply is provided. The VBAT consumption with RTC is around 150 nanoamps typical at 1.8 volt. Three bits are available in the flash option bytes to prohibit a given low power mode. When cleared a reset is generated instead of entering the related low power modes. The microcontroller integrates special means allowing the user to debug software in low power modes. Three bits are available in the debug control register in order to allow debugging in sleep, stop, standby and shutdown modes. When the related bit is set the regulator is kept on in standby and shutdown modes and the H clock and F clock clocks remain on to keep the debugger active. This maintains the connection with the debugger during the low power modes and continues debugging after wake up. Remember to clear these bits when the MCU is not under debug because the consumption is higher in all low power modes when these bits are set. Due to the fact they force the clocks and the regulators to remain enabled. In addition to this training you can refer to the following presentations. Reset and clock control. Real-time clock. STM32 cube MX focusing on the description of the power consumption calculator.