 Hello, and welcome to this presentation of the STM32MP1's Ethernet MAC Peripheral. This peripheral is in charge of the media access control layer of Ethernet communication. The peripheral presented in these slides is a media access controller, or MAC, for Ethernet protocol. It is fully compliant with the IEEE 802.3 standard. With its own DMA and a data rate up to 1 gigabit, the peripheral provides high Ethernet performances. The peripheral is involved in applications based on Internet networks. Such applications rely on the TCP-IP layer model, as presented in the diagram. The MAC is in charge of the link layer of the TCP-IP communication model. Upper layers are managed by software. For example, transport and Internet layers can be managed by the popular lightweight IP stack. Finally, the physical layer, or FI, is supported by external components and linked to an RJ45 connector. The key features of the STM32MP1's Ethernet MAC Peripheral are presented in this slide. The peripheral supports both full and half-duplex modes of operation at either 10 or 100 megabits per second. Auto-negotiation between the peripheral and the external FI enables automatic configuration of the operation mode. The external FI is supported through two interface types, the typical media-independent interface, or MII, and the reduced MII interface that needs half the pins of the MII. Among the advanced features supported by the peripheral, we can list multi-layer packet filtering, management of double VLAN tags, precision timing protocol support with high precision timestamping of frames and support of multiple cues for audio-video bridging, and several network statistics registers available to monitor the connection quality. In addition to the previous features, the peripheral brings several types of heavy processing offloading. It supports automatic management of preamble and start-of-frame tags, checksum checking for received frames and upper-layers checksum's computation, and automatic TCP packet segmentation. Two low-power modes are supported, enabling power consumption saving. The energy-efficient Ethernet mode for power control during transmission and a sleep mode where the peripheral is put on hold, waiting to receive special wake-up packets to resume. This slide presents the offload processing managed by the peripheral on an Ethernet datagram. You can see that most of the non-payload part of the datagram is efficiently managed in the hardware. The preamble and start-frame delimiter, or SFD, are basic synchronization patterns and are inserted or deleted automatically. MAC address filtering is recommended to select only the frames that are relevant for your application. The MAC supports multiple filtering options for unicast or multicast address frames and perfect or hash filtering. Single and double VLAN tagged frames are supported. Double tagging is used for routing complex traffic with two VLAN levels used simultaneously. The Ethernet peripheral supports automatic insertion, replacement and deletion of any sequence of outer and inner VLAN tags. The payload is composed of data from transport or internet layers. The peripheral can filter received frames depending on either port or IP addresses. The checksum is computed or checked for IPv4 headers and the TCP-UDP of the ICMP payload. Finally, the CRC is computed for the whole datagram without taking into account the preamble and the start-of-frame tag. Some of the features listed above are detailed in the next slides. The Ethernet MAC peripheral offers some filtering capabilities that can be applied to the received frames. The different filters are nested. Layer 2 is filtered first with the MAC addresses and VLAN tags. Then the internet layers filter is applied based on IPv4 or IPv6 addresses. And finally, frames are filtered following the port number of UDP and TCP protocols. Any frame rejected by one of the active filters will be discarded and not delivered to the host. For all layers, perfect or hash filtering is available. We have seen in the previous slide that filtering capability on Layer 3 and Layer 4 was available. We will now see that other processing on these upper layers are offered by the peripheral. Checksums of IPv4 header or checksums of TCP-UDP or ICMP data payload are computed by the hardware. These values are then either transmitted in the output packets or compared to the received ones to detect any error in the transmission. The number of the Layer 3 offloading features is the automatic ARP protocol response by sending the device's MAC address to the requester without any software action. Automatic TCP packet segmentation is supported in hardware. The peripheral has the ability to split big TCP packets of up to 256 kilobytes into several smaller packets. The precision timing protocol has been developed to support high precision synchronization between several nodes of an Ethernet network. The targeted precision is approximately one microsecond. This level of precision can only be achieved by hardware support for packet time stamping. For this purpose, an accurate timing reference is maintained inside the peripheral in a 64-bit register. The references can be adjusted by standardized synchronization messages between nodes of the network. The internal reference timing is made available to the system through a pulse-per-second signal that can be output to an internal timer, TIM2 and TIM3, or a GPIO. Timestamp snapshots are also available on up to four external events coming from timers or the CAN interface. These snapshots are stored in a FIFO accessible to the host. The external PHY is controlled by the peripheral through the station management agent or SMA that allows read and write access to PHY internal registers. This interface supports the MDIO protocol on a pair of wires. Read and write operation codes are available. Several media-independent interfaces are supported by the peripheral depending on the selected data rate. For 10 and 100 megabits data rate, the peripheral supports the classical media-independent interface or MII that requires 16 signals between both devices, and the reduced MII that requires only 7 signals and hence allows IO saving. For 1 gigabit data rate, the peripheral supports the Giga MII and its reduced pin count version of the RGMII interface. Two functional low-power modes are supported by the Ethernet peripheral. The first one, the remote wake-up mode, puts the peripheral in a state where only the received path is active waiting to receive a special packet to wake up. This event can trigger a system stop-mode event. All frames except the wake-up ones are dropped while the peripheral remains in this mode. The second low-power mode, the energy-efficient Ethernet mode, works at finer granularity. The link between the MAC and the external FI is maintained in the low-power idle mode or LPI mode, while no data is transmitted nor received. The link returns to normal mode as soon as any data is transferred. There is no data loss in this mode. Energy-efficient Ethernet mode is available only in full duplex at 100 megabits per second operation mode with the MII interface. This slide presents the peripheral block diagram. The Ethernet peripheral embeds three direct memory interfaces for receive and transmit paths with an internal arbiter. In multiple-Q operation, the RX-DMA is shared between the two Qs, while there is one TX-DMA per Q. There are also FIFOs for RX and TX-Qs for data flow management, a media access controller or MAC supporting most functional features detailed in previous slides, offload engines, precision timing protocol, power management and MAC management counters for statistics gathering, a media independent interface with a dedicated block for the reduced MII. An interrupt from the Ethernet peripheral can be generated as a result of various events. All these interrupt lines can be masked and converged to the same global interrupt signal linked to the NVIC peripheral. An interrupt raised in remote wake-up mode is redirected to the EXTI as a special event enabling a full system wake-up. Interrupts are reported from the three main functional blocks of the peripheral, the DMA, the MTL, which manages the internal FIFOs for each receive and transmit path and the MAC itself, responsible for all functional parts of the protocol. The DMA part generates normal interrupts when a packet is received or transmitted. It also raises interrupts for all bus error or buffer unavailability. The MTL block generates interrupts when overflow is detected on the received path or when an underflow is detected in the transmit path. The MAC block generates interrupts linked to PTP protocol settings, MMC counters, energy efficient Ethernet and remote wake-up low power modes. It also transfers the interrupt coming from the external PHI. Here is an overview of the peripheral status in each of the low power modes. Only PMT mode is available in stop mode. In this mode, the peripheral waits for wake-up packets. The Ethernet peripheral is compliant with the following IEEE standards for supporting of Ethernet MAC specification, VLAN, P2P and AVB feature, energy efficient Ethernet.