 Hello and welcome to this presentation of the STM32G0 Analog Comparators. It covers the main features of the Ultra Low Power Comparators and gives some application examples. The two Analog Comparators inside STM32 microcontrollers provide a binary output which indicates if the analogue voltage on the plus input is larger than the voltage on the negative input. It allows the MCU to react when the analogue signal crosses a predefined threshold. The comparator continuously monitors voltage in contrast to an analogue to digital converter which operates in sampled mode. The comparator can be used to wake up devices from sleep and stop modes. Applications can benefit from the flexible configuration of comparator properties which can be locked for safety reasons. Another safety feature of the comparator is its ability to generate a brake signal for timers allowing to safely stop the generation of PWM driving signals. The two integrated analogue comparators can be combined into a single window comparator. The analogue properties of the comparator including hysteresis or a trade-off between speed and power consumption are configurable. It offers flexible interconnections of inputs and outputs allowing the selection of thresholds for several external and internal inputs such as DAC outputs or internal reference voltage outputs. The comparator output can be connected to IOs using the alternate function channels or internally redirected to a variety of timer inputs enabling the brake event for fast PWM shutdown. It's also possible to create cycle by cycle current control or input captures for timing measurements. The Comp X control registers can be locked until the next microcontroller reset. This table highlights the differences between the STM32F0 and STM32G0 comparators. The slide shows the general block diagram of the comparator integrated in STM32G0 microcontrollers. The multiplexes on the left select the voltage sources to be compared GPIOs DAC outputs Vref int with four divide ratios. The output of the comparator can be inverted. When the blank source is active the result of the voltage comparison is ignored and the Comp X value is negated. The XOR gate and the last multiplexer on the right enable or disable the window mode. Then the state of the comparator can be connected to GPIOs, EXTI module to generate a wake-up request or an event to the CPU, timer inputs. Each comparator has a non-inverting input and an inverting input. The NM cell field in the Comp 1 CSR and Comp 2 CSR registers is used to select the inverting input. Each comparator's output can be masked during a blanking time defined by the timer output compare value selected in the blank cell field. The two comparators can be associated to form a window comparator through the win out field. The blanking function aims to mask the output of the output of the comparator during period of times indicated by a timer. This is typically used in the predictive functional control technique. The comparator can be used in the cycle-by-cycle regulation loop for monitoring the peak value of the current flowing into the load. The purpose of the blanking function is to prevent incorrect current regulation tripping due to the use of the PWM period. Short current spikes caused by activating the power switches can produce false pulses on the comparator output, marked by the blue colour on the diagram. These pulses need to be masked by a blanking window to avoid false-fault detection. The blanking window waveform can be generated by one of the timer inputs. The comparators have internal connections with the timer unit. The output can be internally redirected to a wide range of timer inputs for the following purposes. Emergency shutdown of PWM signals, using BK-IN and BK-IN2 inputs. Cycle-by-cycle current control, using electronic timing relay, or ETR inputs. Input capture for timing measures. The upper table is the connection matrix between the comparator and the timer units. The OC-REF-CLR timer input used in STM32-F0 is replaced with the ETR input in the STM32-G0. The connection between the comparators and the timer is generally used for two purposes. Cycle-by-cycle current limitation based on the blanking mechanism. External counter-reset when the voltage drops below a threshold, zero crossing detection, when both are needed simultaneously. The current limitation is based on the ETR timer input and a counter-reset when the voltage drops below a threshold. The current limitation is based on the ETR timer input and a counter-reset is signaled through a timer channel input. The figure represents an example of direct connection between timer and comp unit. Overcurrent limitation uses the ETR input and external reset uses the CH1 input. When combined with a PWM output from a timer, the electrical current control loop is simplified in the STM32-G0 with regards to STM32-F0 microcontrollers. No external loopback is required. T-ONMAN and T-OFFMAN are controlled by direct signals connecting the comparators to the timers. The purpose of the window comparator is to trigger and interrupt if the analog voltage exceeds the line lower and upper voltage thresholds applied to the inverting inputs of each comparator. This event can generate an interrupt through the EXTI line. Two non-inverting inputs can be connected internally by enabling the win mode bit and therefore save one IO for another purpose. The comparator performs continuous voltage monitoring while the ADC watchdogs periodically sample the input voltage. The comparator's power consumption can be adjusted to have the optimum trade-off between the speed and energy efficiency for a given application. There are three modes available, high speed, medium speed and ultra-low power. High speed mode is preferred for power conversion applications, for example a motor control design. The comparator can stay active even if the rest of the system is suspended and the clock is switched off. The comparator can trigger an interrupt on the rising, falling or both edges of the comparator output through the EXTI line. This is required to exit the stop modes. The output can also be connected to the CPU's nested vectored interrupt controller, also known as NVIC. The on-chip comparator remains active in the following modes, run, sleep and stop modes. In standby and shutdown modes it is powered down and must be re-initialised for use if returning to one of the higher powered modes. The on-chip comparator configuration capability allows the user to select the best performance point for the targeted application. It replaces the external standalone comparator thereby reducing the bill of materials.