 Today, we will discuss about designing a transistor in the nanometer regime. There are two important considerations that we will look at today. One we call as channel engineering and the other one is source drain engineering. Based on our discussion so far, it has become clear that if we want to design a very small geometry transistor, in this particular case we are looking at n channel transistor. As the scaling guidelines suggest, when we start decreasing the channel length, this is our channel length. The question is what do we want to do inside this silicon? How do we engineer this silicon? As you recall, the simple scaling guideline had suggested that the substrate doping concentration, which is acceptor impurities in a p type silicon, that should increase from generation to generation. The K is a scaling factor which is greater than unity and every generation, the doping concentration continues to increase. So, we do know that as per the scaling guidelines, NA should increase. This is very obvious, but the question is should it increase everywhere in this region? This is my region of interest that we will look at today. We note that while increasing NA is very important from the point of view of short channel effect because higher the NA, lower is the coupling between drain to source and your V t roll off is not as much as otherwise it would be. In addition, we have also discovered that if you have higher doping concentration, your drain induced barrier lowering is also not as much because your drain electric field is completely screened by higher doping concentration. But are there any downsides or disadvantages of increasing doping concentration of increasing doping concentration? We have mentioned in earlier lecture, there are certainly a few disadvantages. For one thing, your mobility field effect mobility suffers greatly because higher doping concentration in this area especially where the current will flow very close to the interface from source electrode to the drain electrode. There is more scattering because of higher impurity and that is not good. Your current will eventually suffer that is one important consideration. There are other important considerations as well as you also know the sub threshold slope depends on this non-ideality factor which is 1 plus C D over C ox. We want to minimize this 1 plus C D over C ox. In other words, we want to minimize C D. However, increasing N A is not good because increasing N A increases C D and your sub threshold slope also becomes worse. The sub threshold slope increases instead of coming close to 60 millivolt per decade, it will go far away from 60 millivolt per decade because of increased doping concentration. This is also not good. After the other considerations, you see increasing doping concentration is also not good for your capacitance that is more importantly junction capacitance because you have the source drain junctions and these junctions eventually determine these junctions have certain area and that determines your total area of the capacitance and the depletion width will be determined by N A. So, which is also not good because higher the capacitance as you know the capacitance will eventually determine your speed of the circuit and also the power dissipation of the circuit. Because as you recall from our earlier discussion, your delay is C V over I and the C in turn includes the so called gate capacitance, junction capacitance and interconnect capacitance. We are not looking at interconnects now, it is interconnect between one transistor to the other transistor. We are not worried about that, but the C junction will also increase because of increased doping concentration. Similarly, as I mentioned your power dissipation or in other words dynamic power dissipation is essentially given by C V D D square times F where F is the frequency of switching that is why we call it dynamic power. When you are switching, what is the power consumption V D D is the supply voltage for your circuit and C again is exactly the same capacitance and you see higher junction capacitance is not good. So, these are the disadvantages, but we have to increase doping concentration in order to shrink the transistor. Now, the question is rather than increasing the doping concentration uniformly in this entire region, can we do it little bit intelligently? Can we engineer this doping concentration and the answer is yes and that is in fact what we call channel engineering. We would like to engineer this entire region in particular. Let us consider this region going from source to the drain very close to the channel and somewhere in the middle of the channel going deep down inside and I will just take the axis convention here typically I most of the textbook use this you know going downwards I will call it x axis positive x axis and you know going along the channel especially laterally in this direction I will call that as a y axis. So, along the y axis I will go from source which is y is equal to 0 I will have that as my reference and go to L which is the channel length at the drain side and along this depth I will again start from the middle point here which is x equal to 0 and x is increasing as I go down further as you already know this dimension is what we call x j you see and that is your junction depth and that is the value of x coordinate at which the junction is formed. So, with this convention let us look at this you know doping concentration along x axis and doping concentration along y axis. Now, as you know y is going from 0 to L this is your source side and this is your drain side x starts at 0 which is your s i s i o 2 interface that is where I call x equal to 0 to 0 and I go deeper down somewhere out here you will also have your junction depth x j and in this direction I am interested to find out what is my doping concentration. Now, classically what you would think that the doping concentration is constant in the substrate and that is how we derive threshold voltage and so on and so forth. In other words if you look at the doping concentration along x direction it is flat and along y direction it is flat same value if it is 10 to the 15 per centimeter cube this is where I am plotting my n a 10 to the 15 this is a very classical case you know this unit is per centimeter cube. Now, as we already said you know let us say this is what we had in a very old generation 5 micron length transistor as the scaling theory suggested when we started scaling the transistor this should start going up that is what the scaling theory suggest. If you were to start increasing it arbitrarily everywhere with the uniform doping you know it may look like this and it may look like this from 10 to the 15 you may start going 10 to the 16, 17, 18, 19 everywhere in the area of the transistor that we have in this entire region. If you were to do that you know that will be detrimental for your transistor and we do not do that we recognize the fact first of all in terms of let us say going from source to the drain all that we need to do is to prevent this drain electric field penetrating inside the channel. So, where do we want to arrest that field we need to arrest that field at this region right. Once you make sure that the field is sort of constrained there it is not going beyond that then you do not necessarily have to worry about this entire region right all that charge sharing for short channel V t roll off drain induced barrier lowering all that is determined by what happens right here at the edge how far are you letting the electric field penetrate inside you see. In other words the message is that it is sufficient if I increase the doping concentration selectively at this region and not let the doping concentration here go up the doping concentration here is increase selectively to an extent that the drain electric field is suppressed in this region of high doping concentration right. So, that is what is called pocket halos right in other words what we are saying is that we introduce very highly doped pockets these are what are called pockets and they sort of you know are going around the source and drain junction and hence the name halo it sort of looks like a halo around the junction. So, there will be one pocket here there will be another pocket here. So, in other words if we were to look at the doping engineering that we want to do going from source which is x y is equal to 0 to the drain I do not want a flat doping profile instead what I would like to do is a very large doping profile here concentration and let it drop down to as low as you can afford to have and again as I start approaching the other end increase it further you see. So, the doping the message is that the doping along y and I have achieved my goal what was my goal my goal was there is this drain electrode here and of course drain and source can be interchange right this is a symmetric transistor if this is this could be source or you know this could be drain and this could be source and I have increase the doping concentration here ensuring that you know my electric field does not penetrate and in this region I have minimized the doping concentration and hence I will be able to reduce all these detrimental effects right mobility will not be degraded as much sub threshold slope will not be degraded as much and so on and so forth. The same argument holds good going along the x direction as well and what we do here is that we do not do this we sort of do a complement of this in other words here the requirement is as I start going near the channel that is where my current is flowing you see that is where I want to minimize the carrier scattering in a MOSFELF FET device the current is a surface channel current. So, what we do is I minimize my doping concentration here and I will then let the doping concentration go up as I start going down and then let it reach some peak value and again as I start approaching the junctions I want to minimize the junction capacitance. So, again I start rolling of this. So, again in the vertical direction I have a non uniform doping profile which is engineered such that at the interface very low doping concentration as low as you can afford to have. So, that when the carriers are going along the channel at the interface very little scattering because doping concentration is low, but as you start going in you provide excess doping concentration to make sure that there is no punch through from the drain into the channel and again as you start reaching the junctions you start minimizing the doping concentration. And you know in other words again doping along x is also non uniform and this is what we call pocket halos and this we call super strip retrograde channel. Sometimes in literature you see this being abbreviated as SSRC which stands for super strip retrograde channel. What it means is that first of all retrograde meaning that the peak is not at the surface which is what you would have expected the peak would be at the surface, but the peak is away from the surface and hence it is a retrograde profile and super strip meaning that you would like to make it as steep as possible you see. So, that when you reach the surface the doping concentration is minimized. So, by doing this all the all the transistors which are fabricated today not just today you know this has been there for last several generation. I think we started using these you know engineering of channel may be from 0.35 micrometer technology onwards quarter micron technology and onwards certainly we have been using pocket halos as well as super strip retrograde channel. By doing this we make sure that we arrest the short channel effects at the same time we do not end up with having all the disadvantages if we had done a very flat doping concentration. So, now how do we achieve this I mean yes we know that this is desirable, but how do we actually do that. Let us now consider that before we talk about the source drain engineering let us take you know one by one let us first take super strip retrograde channel. Typically whenever you want to you know introduced impurities in silicon you use a process called ion implantation. What it means essentially means is that let us say I have silicon let us say I want to introduce convert this p type doping concentration with appropriate impurities. Certain region of the silicon needs to be converted into p type silicon let us say. What you do is that you bring this silicon wafer into an equipment which is called you know ion implanter as you would have guessed it right ion implanter is used to do ion implantation. This ion implanter can extract the required ions if you want to do a p type doping it may take boron ions which is very typical doping for p type right. You take boron ion and accelerate the boron ion at very very high electric field. So, there are you know lot of knobs in the implanter equipment to set your electric field for example, you know typically you can accelerate it to very high electric field like 50 kilo electron volt or 100 kilo electron volt and so on and so forth right. By having a electrostatic acceleration you give sufficient energy to these ions and they will essentially come in and get implanted into silicon right this is a process of ion implantation. It is like you know shooting bullets you have a substrate you have these ions which are like bullets which are at very high kinetic energy they go into silicon. Once they come into silicon they go through a series of scattering processes because silicon has this regular arrangement of atoms every scattering will decelerate this ion and it will lose its energy eventually it will come to a halt right. So, the ion implantation has two important you know process parameter one is what we call energy how much energy have you given depending on the energy the depth of implantation is determined and the other one is dose how many ions that you want to introduce at a given energy right these are two important matrix. But you see the ion implantation process is always a destructive process right meaning that you implant it and it will destroy the crystallinity of silicon right because it is a high energy ion coming in and it will displace the silicon atom. So, invariably after ion implantation you have to do a processing called annealing annealing is essentially subjecting silicon wafer to high temperature typically of the order of 950 degrees or more the idea is that well you have disturbed the silicon lattice you give thermal energy right this thermal energy will let the silicon atoms to go back and you know sit in their preferred lattice sides. So, that is how you repair the damage now a corollary is that whenever you do annealing there is also a process called diffusion whenever I heat silicon to temperatures like 950 degree centigrade right any impurity inside silicon can start diffusing from higher concentration to the lower concentration it is just analogous to diffusion that takes place in gases diffusion that takes place in liquids except that this is what is called solid phase diffusion when silicon is solid not at room temperature at room temperature things do not diffuse. But if you take it to you know 950,000 degree centigrade then you know impurities and silicon can also diffuse from higher concentration to the lower concentration. Eventually the profile of the impurities that you get inside the silicon is due to a combination of annealing and diffusion and in fact most of the time with impurities with impurities such as boron and phosphorus which are the common impurities which were common impurities for very long time is that they are very light elements as a result of that they have high diffusivity right light elements have you know you can qualitatively imagine very high easy to diffuse whereas, if the mass of the element is very large it is very difficult to diffuse it. So, what is the implication of that the implication is that remember the kind of profile that I want to get along the x direction is something like this this is what we called retrograde channel profile. Implantation as I said will let you determine what is the range what is the peak the range essentially is the peak of the ion implantation where you know there is always a Gaussian distribution whenever you try to introduce impurities through an implantation process not all impurities will go and stay at the same location you know the reason for that is that it is a random process you see the ion is coming in and it goes through a collision the collision will deflect it in any which direction it is a random process. So, depending on how many collision each will see and in which direction it goes some will go far into silicon some will go much earlier they will stop because they will hit more collisions statistically speaking and eventually you have a distribution, but the peak of the distribution is what we call range of ion implantation. So, I could potentially use appropriate energy because range as you know is a function of implantation energy like what I mentioned you know 50 k e v 100 k e v I can choose the appropriate energy and say this is where I want to have the peak, but what I told you already is that after an implantation you need to do the annealing you see when you do the annealing invariably if the diffusivity is very large after annealing the profile may essentially flatten out you know in fact you know it may either flatten out like this because it will diffuse from higher concentration to the lower concentration higher concentration to the lower concentration and rather than having a peak profile you will have a flat profile and this is what you will see invariably with boron and phosphorus because they have very high diffusivity. In order to get a super steep retrograde channel profile what we need to do is to choose the dopants which have very low diffusivity. So, you implant them and when you anneal annealing process should only repair the silicon damage you see annealing is required because silicon has been dislodged from its lattice site and you just you know let the silicon come back to its lattice site. However, the dopants do not diffuse much because they are heavy elements and hence what we do is that instead of boron we use indium which is also a column 3 material instead of phosphorus phosphorus use antimony which is also a column 5 material and this is also a column 3 material. In all state of the art transistors if you are doing a super steep retrograde channel design invariably you are going to use indium for p-type dopant and antimony for n-type channel dopant. In addition to indium you also use you know boron as well because what eventually what would happen is that when you are building the transistor this whole transistor will be built in what is called a p-well and similarly the p-channel transistor is built on a n-well and the well itself has to be very deep you know this p-well has to be very deep I have shown you saying that the whole substrate is p-silicon you know it need not be p-silicon it could be either n or p it does not matter, but then you define the wells of the appropriate concentration appropriate dimensions. So, when you do that well the wells have to be very deep and the deeper part of the well which is to ensure that you know there is no leakage from the n-channel transistor to a neighboring p-channel transistor the depth is defined by a light element like boron because the light element can go far away down because you know same energy light element goes much further down whereas whatever you want to do near the channel you define that with indium. So, today's transistors really use a combination of for example, if you want to do a p-well p-well is what is required to define n-channel transistor this is for n MOS correct use a combination of boron plus indium and boron is defined used to define depth of the well. So, that ion implanted does not have to use very high energy to put indium very deep, but indium will really decide near the channel how should be the doping profile right what I mentioned very low concentration near the surface and you know peaks somewhere in and the advantage now is that if this is your indium implantation and you subject this to annealing after annealing there may be very very little diffusion may be almost negligible diffusion you would still be left with very high peak concentration here very low concentration here and very low concentration here there is little bit diffusion may be you know depending on what temperature what time you do, but nowhere compared to what would have happened with boron and that is what we do here. And similarly for an n-well which is for a p MOS transistor we make use of a combination of phosphorus plus antimony this is near the channel and this is depth of the well again. So, this combination will now ensure that you know I get the required doping profile and I have done the right channel engineering of super steep retrograde channel along the x direction fine. Now, let us look at the pocket halos again this is done using implantation and that implantation process is called pocket halo implantation what is the requirement for us right eventually I do this n plus transistor the junctions and this is p type let us say I have already done the x axis whatever doping engineering that I wanted to do, but it has been done everywhere like this, but now I have to define a non-uniform doping concentration meaning I need to selectively enhance the doping concentration in this region and the doping concentration in this region and where is that region that region turns out to be exactly at the gate edge this is my gate right and this is what we would exploit and what we do is the following right during implantation as I already mentioned you have silicon wafer and you introduce impurities right, but implantation equipments also give you a flexibility to tilt the substrate during implantation meaning the right now the way it is the substrate plane the wafer looks like this right the wafer is flat here and you are doing the you know implantation out here which is essentially yeah you know this is a flat wafer right and the implantation is coming down at an angle which is 90 degree to the plane of the wafer, but I can rotate this wafer during the implantation and then the implantation species is coming at an angle to your wafer right. So, I make use of this parameter of implantation which is called a tilt angle wafer is tilted. So, if you were to do a tilted implant right let us say I do a tilted implant in which case I rotate the wafer with respect to your incoming beam right. So, rather than rotating the wafer I will just show you the incoming beam which is coming at an angle correct depending on how much is the tilt the beam will be coming at the required angle right. Now, let us say I tilt the wafer by 45 degree then this beam will be coming at an angle which is 45 degree correct fine. So, what I do is the following you see this is p type which is let us say a combination of indium post plus boron which we have already discussed I have already defined in the x direction and selectively in this region I need to enhance my boron concentration. So, what do I do first I pattern my gate electrode gate oxide is there gate poly silicon or metal whatever gate you know thick metal or poly silicon electrode is patterned here. Now, I use this itself as a mask. So, this is sort of a self aligned process. So, what I do I introduce boron at an angle boron is coming at an angle when it is coming here it will get inside you see the junctions are not yet formed the junctions will be formed much later in the process in one of the future lectures we will actually go through the entire process sequence of CMOS flow. So, right now the way the wafer looks is that you are you have done the initial super strip retrograde channel let us say that is your boron plus indium implant it has been done boron plus indium and then you defined your gate oxide defined your gate electrode and now you are doing this angled implant. When this angled implant is coming in this region this whole thing will be trapped here because it will not go through the deep the depth of this poly silicon it is fairly thick, but here it will just come in here. So, in this region exactly where there is a gate edge I have been able to introduce the dopant just in this region, but excess doping has not come in this region because this whole thing got trapped, but this has come only at the drain end, but I also need to do it on this side as well. So, what do I do I tilt the wafer the other way and get the implantation done in this direction. Now, when the implant species is coming this will get inside here, but it will all be get getting trapped in this region. In other words what you have been able to do is that wherever you had this gate edge only in this region you are able to increase the doping concentration selectively. Of course, the doping has come in this region also, but I really do not care whatever has come in here as you know the whole thing is coming at an angle nothing to stop here this will be coming down here also, but subsequently this region will be counter doped and I will make n plus junction there I am not really worried about that, but this region was the important region for me where my p type doping concentration had to be increased and I have been able to do that whereas, this region the whole boron got trapped here and it got trapped here and it did not reach this point at all. So, in the middle of the channel I maintained the low doping only at the edge where eventually my source and drain will come you see as I mentioned eventually my source and drain I will counter dope is at n plus I will also dope it as n plus. So, when I go from 0 to L you have very high doping here a very high doping here and this is what you do in terms of engineering the pocket halos. So, the pocket halos again to sort of summarize pocket halos are done with tilted implant. So, you tilt the wafer you know you implant at an angle as I said you know rather than in the pictures I showed wafer flat and this beam coming at 45 degree, but in reality the beam is always coming down and you tilt the wafer like this when you tilt the wafer one side of the all transistors got implanted, but the other side is not implanted. Then what you do you rotate the wafer and again tilt the wafer in other words you are implanting to the other side as well and that make sure that the implantation is done on this side here in the picture down here and the implantation is done on this side as well and it turns out when we do the circuits we do you know all these transistors in what is called you know so called Manhattan geometry right we lay them the transistors are laid either along the x axis or along the y axis. So, what I mean by that is that if the transistor in the top view when I am looking from the top remember this is my transistor gate let us say and the source is here and the drain is on this side and this is the width of the transistor this is the length of the transistor right the transistors are either put in like this or the transistors could also be put in like this because it is a large circuit you see a millions of transistors, but they are not never put it any angle that is essentially with this kind of consideration right. So, now what we do we tilt the wafer and do the implantation here we rotate the wafer by 180 degree and do the implantation here and we again rotate the wafer and do the implantation in this direction and do the implantation in this direction all these are angled implants right. So, they make sure that wherever you have this gate edge you see at all the gate edges irrespective of whether the gate is aligned like this or the gate is aligned like this you are always doing the angled implant towards the drain side towards the source side to cover all vertically aligned transistors and again at this angle and at this angle again source and the drain of this transistors of all horizontally aligned transistors right. So, by having this you know very involved and implantation process where you rotate the wafer tilt the wafer and introduce the dopants at the required angle you are able to define the pocket halos right, but this is now a routine process right you know all the transistors routinely go through this process right. So, by doing this you know we are able to get both the pocket halo implants as well as the super steep retrograde channel implant. So, this is what we mean by channel engineering the next important aspect is the source drain engineering. So, again here what does the scaling theory tell you this is the junction depth with technology generation scaling this x j should decrease very obvious we have already discussed the reasons for that lower x j instead of x j being here if you have x j which is extremely shallow which looks like this n plus n plus very shallow junction x j very low volume for coupling between drain to source. Your short channel effect goes down v t roll off is not as much we have already discussed that based on a simple model called yaw's model also the drain induced barrier lowering will also decrease, but there is a problem here there are couple of problems actually. What are the problems you know just as we were asking the question increasing the doping everywhere are there problems yes there were problems and we use channel engineering to overcome that. So, disadvantage here stage of x j coming down first the parasitic resistance of the transistor increases what is the parasitic resistance we have already sort of discussed this my transistor which is gate controlled is only this region correct. So, if you were to write a circuit equivalent eventually your transistor contact will come somewhere here and the transistor contact will come somewhere here a metal contact we have seen this in one of our earlier lectures. I have shown you this if this is ground potential at the metal then there is this resistance and then this is a transistor which is controlled by gate circuit schematic and then again there is a resistance and this eventually goes to your supply these resistance are killers right this is what we call parasitic resistance and shall over the junction versus the parasitic there is another problem. And that is reliable contacts contact formation reliable contact formation is an issue what do you mean by that you see eventually you make a junction here let me just blow up that region right just that region here. So, this is the junction this is n plus p junction and I need to put metal here when I put metal and after that it goes through lot of thermal cycling you see invariably there will be what is called a metal spiking this is you are putting the metal. So, let me just sketch it with a different color this is metal and the metal to silicon this junction is very rough it is not atomically you see there is going to be what is called this spiking or undulations here. If you have a extremely shallow junction you may actually spike through the junction then you do not have a you know reliable junction which is not good. So, this is the problem right again you know we need to really do a balancing act I need to be able to shallow junction at the same time I do not want to encounter these problems of higher resistance and dealing with the non reliable unreliable contact and so on and so forth right. So, this is where I do what is called source drain engineering. So, in other words when I build source and drains of the transistors ideally I would have like to build a very shallow junction which would look like this, but there is going to be lot of problems with this kind of a shallow junction what I do I do a via media I do something which would look like this. So, this is now n plus this is n plus this is p silicon and this is also n plus it is the same n plus here, but you see the junction depth here which I will call x j 1 is less than this junction x j 2 let us say x j 1 is less than x j 2 wherever it matters what is the important thing that matters it is at the edge of the gate the drain how does it couple into the channel. So, in that region you make it shallow. So, that this is the region which is trying to couple to the source and you know trying to influence and this region is far away anyway this is the influence of this region on this is not as much. So, this is what is called shallow extension shallow extension has a junction depth x j 1 and then as I go away from the gate edge this is my gate you see this is the gate edge which is 0 this is the gate edge which is l this is the source side this is the drain side as I go away from the gate edge I make deep junctions where the junction depth is x j 2 you know this is something which will help you in addressing both the issues your short channel effects will be minimized as per the scaling guideline you have anyway decrease the junction depth because this is the region which will for all practical purpose control your short channel effect drain induced barrier lowering and so on and so forth. At the same time eventually you will make the contacts here and in this region you know you have deeper junctions and also in this region your contact resistance will be lower your parasitic resistance will be lower because you have deeper junction. So, this is what you do to ensure that you have best of both worlds you do a very reliable short channel you know sub 100 nanometer transistor using this kind of source drain engineering. So, none of the transistors today have flat source drain you know the source drain profile does not look as if you know you have junction which is going flat and then you know going up here it always looks as shallow extension there is a shallow arm which is touching the edge of the gate. The question is how do you realize this? This is realized the shallow and deep source drain is realized using what is called spacer technology. What it means is the following goal is to get this junction, but just as I mentioned all the impurity introduction is done using implantation correct. I have already done p type implantation here you see p type well has been defined here with the super straight retrograde channel and the pocket hellos here and pocket hellos here all that is done. Now, I need to form junction and junction is done by using arsenic implantation n type implantation for n channel transistor. So, the idea is to do two step implantation the source drain implantation is a two step process first one is what is called shallow implant and the second one is called deep implant. Now, when you have this kind of a structure when you do shallow implant the shallow implant can go everywhere it does not matter you know the shallow implant can come even here because any way you want to dope it very heavily n type correct. So, shallow implant should come everywhere again when you are doing the shallow implant whatever is coming here is trapped in the gate you see and that is how you do not get this n type dopant coming down here that is why it is called a self aligned process. The gate edge defines where the source drain junctions get formed and hence the name self aligned process. In fact, during the same process the poly silicon in a poly silicon gate technology the poly silicon also gets doped n plus in a n channel transistor. So, this is a shallow implant shallow implant will put your implant dose species only at this depth, but now I need a deep implant also, but when I do the deep implant I want to protect this region. If I can somehow define a region here some insulator and then after defining this insulator you do the deep implant. So, when you do the deep implant again the deep implant is coming down everywhere because this has higher energy. You engineer the implant energy such that and this thickness of the spacer such that anything that is coming here will get trapped in the spacer and only here it will go down. So, what have you done here you have been able to protect this region by having the deep implant go in and hence whatever was implanted earlier for the shallow range is intact. Whereas, here in addition to the shallow range there is a deep implant and hence you have deep junctions. Here you have shallow junctions here you have deep junctions. So, if you can this is what is called spacer. This is a region which you know puts this deep implant away from the gate edge by a required dimension. How much should it be and all that is a detail of a transistor design. So, the spacer typically is silicon nitride and it offsets deep source drain implant away from the gate edge that is the whole idea. So, at the gate edge where it matters shallow junctions you will retain shallow junctions, but away from the gate defined by the spacer thickness you have deep implants. So, this is essentially done you know with the series of you know some very simple, but very intelligent process steps. What is done essentially is that you have the silicon wafer you have already defined this gate. Gate is defined using photolithography you see depending on what is the length and width of the gate you have printed that already. This is SiO 2 and this is a gate either poly silicon or metal depending on which technology you are looking at. Now, what you do is that you do a insulator deposition here and that is done using a process called CVD or chemical vapor deposition. In fact you know either make use of just a simple low pressure chemical vapor deposition which is called LPCVD or PECVD which stands for plasma enhanced chemical vapor deposition. One of the key aspects of CVD process is that the process is what we say conformal meaning wherever there is edge the deposition happens along all the edges the contours are preserved. So, typically what you do is that if I want to build a silicon nitride spacer I could have directly deposited silicon nitride, but eventually I want to edge silicon nitride. So, while etching silicon nitride the selectivity of silicon nitride edge to the silicon because I have to stop on silicon you see right is not so great. So, you do a very thin silicon oxide first of all through CVD. So, what this silicon oxide CVD does is that it deposits silicon oxide everywhere this is a very thin SiO 2 you follow it up with a thicker silicon nitride. So, your silicon nitride will look something like this as I said it follows the contour all it means is that the reaction happens through chemical process chemical reaction at the gas phase you introduce you know for example, for silicon nitride you introduce dichlorosilane along with ammonia dichlorosilane silicon in dichlorosilane reacts with nitrogen in a ammonia and produces silicon nitride and that silicon nitride will come and condense on top of all these open areas right that is why this CVD process is conformal right. So, the corollary is that some that is something very interesting let us say I have this gate which is gate stack this is called gate stack oxide plus key of course, silicon oxide is extremely thin let us say this gate stack is of the order of 100 nanometer which is 0.1 micrometer tall that is how the gate stack is right and let us say I want to offset this you know to the left by another 100 nanometer let us say right the way I have drawn it may be this is little bit thinner than this let us say 15 nanometer is the offset that I want to provide right. So, it is not to the scale do not worry about that too much let us say I have deposited 15 nanometer it will be 15 nanometer everywhere except here very interestingly it will be not just 15 nanometer it will be this 100 nanometer plus 15 nanometer it will be 150 nanometer because what it did was that it sort of try to conform to this profile right in a process the deposition was happening from all directions right this is how the CVD deposition was happening you see and as a result of that if you look here you have much thicker thickness of the silicon nitride if this is 15 nanometer if this is 100 nanometer this could be 150 nanometer you see and it is only at the gate edge because it was trying to follow this contour this is a blessing for us now what we do we do what is called an anisotropic edge of silicon nitride anisotropic edge is a directional edge it happens only in a vertical direction it does not happen direction whereas isotropic edge is you know etching in all direction if you do etching in wet chemistry it is all most of the time you can also have anisotropic wet chemistry, but most of the time it is isotropic edge, but if you do dry etching it is invariably what is called reactive dry etching is an isotropic edge. So, what I do now is h a 15 nanometer silicon nitride, but that is done anisotropically if it is done anisotropically the 15 nanometer is h d here 15 nanometer is h d here 15 nanometer is h d here this you are left with this region you see because this region had much thicker silicon nitride and now I have got this nice little regions here which we call spacers which are exactly aligned to the edge of the gate this is not done using lithography step you see that is why we call it self-aligned if you do it with lithography that is more complicated process and then you do the deep source drain implantation. So, and hence you know the sequence of processes will be essentially c v d of thin oxide thin oxide just gives the edge selectivity against silicon nitride edge then c v d of silicon nitride then anisotropic edge of silicon nitride that defines the spacer follow it up with deep source drain implantation. So, this sequence of simple processing steps will ensure that you have a very nice self-aligned space and you know you have a very well behaved junction profile which is shallow here spacer is defined do deep source drain all the impurities are trapped here it comes only here and deep junction and shallow junction correct. So, then let us just recap and summarize what we have done today right we recognize that we need to do a channel engineering and source drain engineering only then we get the best transistor performance. So, channel engineering is done using two different techniques one is what is called super steep retrograde channel this is engineering the channel in the x direction that is vertical direction and then you have pocket hello that is engineering the channel in y direction and this is done using the tilt implant and this is done using heavy species like indium and antimony. And the other important thing is the deep source drain and shallow extension and deep source drain this is your source drain engineering this is your channel engineering here first you do a low energy implant g arsenic implant then do a spacer and then do the deep source drain implant. This will ensure that you know you have a very well behaved transistor which gives you the nice short channel performance and your mobility will not be degraded your drain induced barrier will not be worse contacts have very low distance and no problem with junction spiking and so on and so forth. So, let us stop the lecture today and you know we will continue further in the next lecture.