 Thank you, thank you for the introduction. So a lot of the talks that have been in today's room have been about PCB design tools and things like that. We're going to go even lower than that. We're going to talk about building chips, ASICs with open-source tools. OpenPetan is not a open-source CAD tool, but it is being used by a lot of open-source CAD tools right now as the test suite for that. So what is OpenPetan? Well, OpenPetan is the world's first open-source general-purpose multi-threaded mini-core, but when you think about it, it's really a best-of-breed mini-core architecture design where you have lots of different cores, general-purpose cores that you can put together, all written in Verilog HDL and all open-source. So our design, the core of it, or sorry, not the core, the most of it is BST license, and one of the cores is GPL and some of the other cores are Soderpad. But we can actually eat in lots of different cores now. So now we actually have 10 different core types, microprocessor core types, excuse me, with four different instruction set architectures. It was designed to be scalable. So it scales up to about a half billion cores, but I don't really recommend actually trying to build that. But the secret sauce here is that you can actually have a configurable and cache coherent interface where you can hook together lots of cores in a, well, I'll show some pictures of this in a 2D mesh design and build very large chips. It's all open-source, so you can use this in your open-source CAD tools and in fact, I will be talking about the end of today's talk, that there is a big movement now for open-source EDA hardware tools, and they're using OpenPetan as the development tests for that, and I'll talk a little bit about that. Some other sort of things as I said, sort of chip level, we've actually built some of these chips and I'll talk about that in a second. But from a simulation perspective, we support all the commercial and open-source simulators these days for Verilog. So we have Icarus Verilog and Verilator are some of the two most popular open-source EDA Verilog simulators these days. This design has been ASIC verified and FPGA verified, and we'll talk about that in a second. And we've done very careful power analysis on the actual ASIC we've built and cross-referenced that with the open-source design, so you can go and use that to make sure your tools, your EDA tools are doing the right thing. Because that's really important is you want to have sort of a design reference of maybe something that may have went through a commercial tool and see if that actually you're getting good quality results or some of that from this whole thing. And I should also say this runs full-stack Davion Linux, it's a full working many-core design. We've built chips with 25 cores, we can scale up to many, many more cores. So that's OpenPetan. Well, we took OpenPetan and we extended it and started adding more cores. The original OpenPetan actually used an open spark core, so spark so open instruction set that the old Sun systems used to use, and Sun had open-source that at some point. And now we've extended it, risk five is sort of becoming hot these days, so we wanted to add in sort of risk five support. Because in reality, OpenPetan, we don't really care that much about the core, we care much more about the uncore and building a scalable uncore. So we took in a collaboration with ETH Zurich and the pulp team and integrated the Arian core. So the Arian core is a general purpose 64-bit risk five processor, which we've integrated in collaboration with ETH Zurich and the pulp team, as I said before. And what was especially really kind of cool about this is we were able to do this integration and it took us less than six months from the time we started integrating our registered transfer language Verilog code to the point where we actually had working design in FPGA booting SMP Linux. So these are silicon proven designs and that's something you really need if you're gonna go build and use your open-source CAD tool is, you know, is this real designs, is it not just synthetic designs? I'll talk a little bit about synthetic designs in a second of why that's not really great for using for your CAD tools. So what are the sort of chips we've built? Well, we built the PTOM processor at Princeton, which is a 25-core, many-core implementation of this. It uses three on-chip networks, a directory-based cache coherence system. This was taped out in IBM's 32-nanometer process a few years back and it was about 460 million transistors which is one of the largest academic chips ever built. At ETH Zurich, the Arian team has taped out a couple different variants, one named Poseidon, one named Cosmodrome, where Arian shows up as processors used in the ETH Zurich work and now we're actually working to build chips together and we're gonna be taping out this year some open PTOM plus Arian designs in a 12-nanometer process. So as I said, you wanna not just target or be a good open-source design just for ASIC design, you also wanna be good for the FPGA world. So we map to a bunch of different FPGAs and we've shown this, so we have things from sort of one, two cores and relatively inexpensive boards all the way up to many cores or, well, 12 cores in sort of quite expensive boards. And the other thing that we've been talking about recently and have done recently is we now have this on Amazon F1. So in Amazon AWS or Amazon Web Services, you can rent a FPGA in the cloud for about a dollar or 60 an hour. I don't know what it is in the European world if they have actually the F1 instances that might just be in the States, but you can use those and rent it and then you don't need to own a $8,000 test board to go do this, you can go rent some $1.60 an hour prorated board, which then you can go use and actually develop and sort of test out these types of things. Okay, so what's sort of the design system here in open PTOM? As I said, it's a 2D mesh structure, so each of these things is a tile. Inside of a tile, we have a network on chip routers, let me zoom in here for a second. So we have three routers, we have a slice of a last level shared cache with a directory, and then we have a private cache and we have the core here. And then we have a lot of off chip chipset stuff, which is actually really helpful if you're trying to go build a CAD tool, you don't just want cores and you just don't want interconnect, you want sort of everything to go test your CAD tool. So we've got a lot of feedback from people who are using this, that they actually want the variety of all the things that you could possibly sort of put together. So this is sort of the open PTOM system. Nowadays we're doing open PTOM plus Arianne, so literally we just sort of took open PTOM, or sorry, took the open Spark core, ripped it out and put in the Arianne core. And there's a lot of work that went into that, it's not quite as easy just ripping it out and putting it in. But we have a paper coming out together with the ETH-Zeruk team at ASPLUS in two months where we talk a lot about how to go do that and build the infrastructure where you can plug in lots of different core types, which are vastly different. Okay, so this brings me up to the sort of CAD world here. So we've heard a lot about EDA tools for PCBs. What's the state of the art sort of in the chip world? Well, they're used, but maybe not anyone's actually sort of taping out chips right now with that. And that's sad, in my opinion. And what's missing? Well, we've had a lot of tools from academic groups for verification, we have open source flow for some very small FPGAs these days. But in reality, we want to sort of get to the point where we can tape out large chips, least academic chips, or maybe commercial chips with a full open source EDA tool flow and for the chip side. So when people have traditionally tested these things, they have a lot of times been using sort of old industrial designs to go do their test. And one of the things, or they're using old academic designs. And one of the biggest problems here is they're really limited in scale. So if you go look at sort of the designs out there that people have used traditionally to test EDA tools in academia, they're using sort of example designs, or they're using very small designs, or they're using obfuscated designs that are coming from industry that are not particularly open or realistic. They're typically very synthetic. And we see OpenPetain and OpenPetain plus Arianne as a mechanism to get real designs that people have actually taped out and can scale to big design points, going through large chip flows, open source chip flows. Okay, so what is really needed here to be a good benchmark or a good use case for open source EDA chip CAD flows? First thing you want is you want a lot of different design variety. And we provide that. So we have big cores, we have small cores, we have caches, we have interconnect, we have actually a GPGPU which is connected into this. We have a different IO and we now have been adding different accelerators into this design mix. So you can basically build complex SOCs out of this design point and we're going to be taping out some of them so that people can use them as reference points. You also want a lot of configurability. So you want to be able to change up different design points because we've heard back from the people that are sort of using this that you want to be able to sort of try different scale and try small scale first and then as you get bigger and bigger and you want to like look at what's going on, you want to try and stress your DRC checking at the scale but you also want to test it in the sort of small case first. So we want to have this different scale and we can build big designs or big real designs that we'll work in and at least in simulation run real programs but no one has a 500 million core design really out there yet because Moore's law has ended and you can't go build chips that big. Okay, so in open pizza, it's not just Virolog. We also give out all of the accoutrements you might need. So we have verification test benches. We have over 8,000 test cases. So if you're building, for instance, a open source verification tool that does the CAD side, you have test cases for that. We also have the power analysis and thermal analysis and we have some PCB designs that for those of you who do build PCB designs, you should please take a look at our boards as input for that. They're pretty complicated designs. So they're like 14 layer PCBs that are, but they're all open and out there if you go to our website. So this is an example of one of the boards here, pretty complex test board that we use to do this sort of careful power analysis. And we've taken this whole piton chip and done careful power analysis and sort of come up with good ground truth. So what is a good ground truth here? So for instance, we measured the energy per hop on your network on chip. So if you're gonna build a best of breed network these days, you can go and actually go look at our paper and it'll tell you sort of how much energy is used for that. And in reality, it's about eight, you can go about eight hops on our knock or network on chip for the energy equivalent of one, let's say ALU. And that's a bunch of the myth of that knocks are really expensive from an energy perspective, it's just not true. Also, we've done a thermo analysis, sort of you can see the nice thermal pictures here, but we've also sort of looked at how much energy it takes to do loads versus stores and different instruction energy usages. And it's really important that this is open source because when we were doing this, we were doing the characterization, well, we designed it so we can go look at it. But if it wasn't open source, it wouldn't be that useful to have these sort of on chip network energy numbers and instruction energy numbers because you wouldn't be able to go look in the design. But because it's all open source, you can go look at it. Okay, so this brings us a little bit back to the EDA tools here. We use a lot of these tools and this is actually a part of a big DARPA program called IDEA where people are building lots of different CAD design tools that are open source and we're the design advisors. So we're giving a lot of this advice and designs out to the users. So we use lots of different open source tools here and we're not just using it but we're actually contributing back. So we've actually filed a bunch of bug reports against all these different open source tools here. And we really need, as just going back to sort of running out of time here, but to sum up that we wanna go back to sort of think about what do we need to have a full open source chip CAD flow, which is a lot. There's a lot of problems you need to go solve there. So actually the right here is the picture of our CAD flow we use sort of commercially and then we're sort of taking all that input and thinking what do we need in the open source world. And you need, you know, hierarchical synthesis, you need, you know, two past designs, you need to be able to do engineering change orders and you need, you know, good support for gate level verification. And this is all these things that a lot of these open source tools don't currently support. So what is missing and what is sort of coming along here? So I'm gonna make a plug for actually two programs that are not mine, they're not collaborators, but they're people I know well. So the first is UC San Diego led by Andrew Kong has been building this thing called Open Road, which is the closest that we actually have today to a full chip EDA CAD flow. And we're working with them, giving them designs that they're actually gonna tape out and then we're using their tools and we're gonna tape out some chips with full open source chip level EDA CAD tools. Also, the University of Washington as a subcontractor under my program has been building a basically a packaging of those tools to go build a full flow because it's not enough just to have the tools. This is something you learn as you're sort of in the chip business is the tools are just the tools. The glue that holds it together, if the flow and how do you put together the tools and how do you use all the flags is actually more important basically than the tools or just as important as the tools because it takes years to sort of develop. So we're expert chip designers and we're using these tools and sort of building that flow for the open source world. And Mike Taylor's group at the University of Washington has released that down here using the Open Road package together with a 45 nanometer fake library that's free that people can use to go test this out together. What's missing? Okay, so let's say the Open Road design is the most advanced sort of chip level open source CAD tools out there, but there's still a lot of things missing. So first of all, there is no DRC tool for chip level DRC that exists today. The DRC decks are really complex, especially we're taping out stuff in 12 nanometer. It's all FinFET stuff. The rules like you go read the manual and you can't even understand some of the rules, right? So the very complicated DRC decks. So we need a DRC tool. Second, you know, YOSIS is great, but we need YOSIS to be even better. We've found lots of problems with YOSIS in particular. I mean, it's not just like system barrel log support. Let's say we get around that. But, you know, we've seen recently something where their way they do asynchronous clocking just doesn't really make sense. So it's even for, you know, synchronous circuits like the asynchronous reset just just kind of doesn't make sense. And then parasitic tools, better system barrel log support. That's actually coming along with the faster than I was expecting. And then things that people don't really think about is sort of parasitic extraction at the chip level. I think there's a talk about parasitic extraction or 3D field modeling here in this session. But at the chip level, it's actually pretty, it's a slightly different game than the board level. And then power grid and signal integrity issues. So we're building a billion transistor chip with the open source open flow tools. We're taping this out in Global Foundry's 12 nanometer. We're really excited to go do this. And then I want to make a final plug here for we are also here today as part of the decades project, which I also lead now in the DARPA SDH software to find Harvard program, where we're also looking at all these open source designs and the open PTAN design used to go build a heterogeneous many core platform. Okay, so we have a whole community. Think about our time, but you know, you can go to our GitHub page. I wanted to acknowledge all the great students that have gone into this. We like to go do fun things. We went camping at the Grand Canyon this year and the Ariane team and the University of Washington team. And then finally, open road is doing some really great stuff. You should all go check out open road. Okay, that's the amount of time. So I will end there. Taping out these chips for validate your research, I guess. Is that why that you do the actual like silicon tape out? You're saying why? So the question is why are we taping out chips? I guess I'm trying to get a sound. Okay, so I guess I'll repeat the question. You know, why are academics building very large billion transistor chips? And you know, when does this transition to industry? I guess is the question. Yeah, so my research is computer architecture primarily. So we want to test out new computer architecture ideas. You can simulate that, but a lot of times the intuition is wrong from the simulation or you miss a lot of details when you don't actually go implement it. So a lot of people do sort of software level simulation of architectural ideas and it doesn't capture enough of what the real problems are when you actually sort of physically build it. So that's sort of the one answer, the commercialization. Question, I've commercialized things I've built in academia before. So many years ago in graduate school I worked in the MIT raw processor which got commercialized in the Tyler chip. So things can spin out. In academia, that's not our goal. Our goal is yeah, you know, we get back, you know, 40 to 100 die. And we typically use shuttle runs. So shuttle runs or multi-project wafer aggregation is where you have lots of different designs that get aggregated together. So you're wearing an Oshpark shirt. Well, Oshpark kind of does the same thing at the board level. But at the chip level, that's pretty common. But then, yeah, you can go commercial. I mean this stuff's sort of commercial level ideas here, but it's really a test on new architecture ideas. It's a great question here. So, oh, sorry. How, as an academic, how do we interface with the foundries and how do we get the PDKs? And it's not just the PDKs, it's also the intellectual property that you otherwise need. So the PDK is just the design rules you also need like standard cells, RAMs, IOs, PLLs, if you can get one of those. Things like that. So, relationships. So yeah, we license it. Typically a lot of stuff is, you know, free for academic use, but there's also a lot of restrictions on it. And yeah, you need to sort of work through that. It's not easy to get. The horror thing maybe than just gaining access is gaining access to something as advanced as like 12 nanometer. So a lot of the foundries will not give academics access to anything that's sort of near the bleeding edge. And that 12 nanometer, at least for global foundries, is their bleeding edge. So yeah, those relationships, you have to know, you know, people, I'll put a plug in here. I know Metro's sitting in the back of the room. There's maybe some opportunities for other free PDKs coming along. That's a problem. It's their proprietary IP of, you know, what is design rules for a PDK? And I don't know, that's a hard to solve problem to make that open, yeah. So maybe you can do that for like old designs. Old, yeah, things that I've heard floating. Okay, thank you so much.