 So, welcome to this lecture on advanced digital system design in the course digital system design with PLDs and FPGAs. The last lecture we have looked at the VHDL coding of the finite state machine or controller. Basically we have looked at the various ways you can code it, code the FSM and we have taken shown some simple example to illustrate that coding styles. There are various ways and some schemes of certain quirks or trouble it brings like synchronous reset. We have handled that situation and today we will continue with the issues with the finite state machine. Before that we will have a quick run through the last lecture slide to be in sync because that may be useful even in this lecture. So let us turn to the slide of the last lecture. So here we have looked at the block diagram of the state machine, a 3 block diagram we have first looked at this and we said these inputs, clock, reset and output definitely clock and reset normally come from outside. So they can be ports sometime if it is internal it can be signal. But input and output if you are testing it stand alone then it is port but many times when you are integrating with the data path it could be ports or signal maybe some input is coming from outside so that could be port. And very important thing though we said that you can adopt various ways of coding the finite state machine. You have to choose the style as prescribed by the specified by the synthesis tool. The basic idea is that synthesis tool should be able to infer that this constitute a finite state machine so that the FSM specific optimisation the problem solving can be done on this structure otherwise if you just code this is a logic and this is flip flop and this is logic then the implementation would be correct it will work perfectly. But the synthesis tool will not be able to do any FSM optimisation or any issue it can normally solve it cannot be done. The example is that we have talked about the state diagram optimisation unless the tool infer that it is a finite state machine. The state diagram optimisation cannot be done there will be redundant states unnecessarily wasting area in the next side logic and output logic and so on ok. We have looked at the various ways and here in this three block we could have this written in a process this in a process this can be written in a process if the number of outputs are greater than the number of states. It can be a concurrent statement if number of outputs are much less compared to the number of states because then there are only two outputs you need only two concurrent statement but suppose there are seven states you may end up writing a case with seven when where and only two outputs are specified not very kind of concise coding though the hardware wise it makes no different. But it is a long code that is why we can write concurrent statement we also said that you know you can combine these two in a single process because in VHDL you can specify a set of registers with the preceding logic in a single process. So that can be done in that case you have a process for this two blocks together and with a process or a concurrent statement set of concurrent statements for output logic and you can include the asynchronous reset here along with the flip flop if it is synchronous reset it is included here and when you combine as I said when you combine both together there is an issue we have discussed that I will just throw light on it and we also said normally when you code the next state logic we write a process with the present state as input and in the sensitivity list and all the inputs because these two are the input to the block and we say case present state is and for each state we specify the transition using if okay. Similarly for the more kind of output you can say case present state is or with select whichever one you use again you can use if for the melee output under the case and so on and this is a process where use the if statement with the reset and clock event or rising edge clock for the flip flops okay. The next possibility is that we come to a two block view where the next state logic and output logic is combined into a single block where the outputs are next state logic and the outputs. So now you can write this in a single process and flip flop in a process and flip flop is as usual but here again you do a case present state for each choice you specify the output if it is more output straight away and melee then you can write an if then kind of structure and for the transition under each state for each when statement of the case you can specify the transition various transition using the if. So one advantage of writing this way is that when you have a state diagram like quickly looking at the state diagram you can complete the whole logic in one shot okay. So that is one advantage of writing it together but if you write as in early then when you write the next state logic coding you have to keep the state diagram run from top to bottom then again come back you know write the output logic and top to bottom you write and when you debug if something goes wrong depending on where the trouble is you have to go through both code okay. I mean these things are come with experience and for some it occurs naturally those who are very systematic sometime by their habit they stumble upon these kind of advantages but then it all shows that you need some kind of planning experience because even writing the code though they are equal and some style of coding is helpful in a quick kind of design debug and things like that you should keep in mind. And we have looked at the problem of a sequence detector mainly as an exercise not as a serious kind of design I do not think you need to use an FSM based sequence detection in communication okay. You can do better than that you can do much simpler schemes than doing this and we said it is an overlapping detector that means like in the case of 101 you know you have a 01 here then the 3, 4, 5 also form a detector sequence detection and we have seen the kind of the state diagram and we have seen the coding the main thing is that the library entity and the most tool allows you to define an enumerated kind of data type for this and define the present state and next state as that type then you write a process for next state logic with the present state and inputs in this case only one input is there inputs in the sensitivity list then you go state by state case present state is when a then you use if on that to specify the transition important thing is to do all the transition if else everything do not think that because you are in state A you do not need to say else next state A that will cause implied light so you continue through and the flip flop is you know like a nursing runners reset you know how to write that if reset then present state is starting state or upon the clock present state get next state and when you write the output as a concurrent statement you can use when else or with select it is with select you say with present state select or with when else you can write like that and we have seen the next state logic and output logic together only difference is that in the case of each choice of this present state you specify the transition as well as the output okay. And when it is more there is no condition on it when it is melee you can write a symbol logical condition here if it is simple case or you can use if or case or whatever is appropriate thing to use at that point in time the flip flop is same then we have seen a melee kind of machine for the same problem and we have combined the next state logic and output logic and you can see that the detect here is written as a melee type detect gets dean. That means if dean is 1 detect is 1 else detect is 0 and many a times when you can write it in a very straightforward kind of logic is better to write like that sometimes what happens is that people get used to this syntax and even for simple things like this one tend to write the if saying that if dean is 1 then detect is 1 else detect is 0 and all that and forget all about what could be the hardware you know it is nothing you know it detected here it is a decode of C which is in our case maybe q1 bar q0. So in this case in the melee machine we are combining the next state logic and output logic in a process and the code is similar only thing is that we have this detect which is written as a part of I mean detect as a function of dean. So when you decode it is like you know the state C and dean is a detect so it is q1 bar q0 and dean okay and it is better you remember these basics always what happens is that when you want danger with the more and more sophisticated tools and these kind of languages that you tend to forget or tend not associate the hardware with it and people like I have seen students writing this simple thing as if dean is 1 then detect is 1 else detect is 0 and so on. And forget what is the hardware not a good thing I mean I have asked some students what is that hardware what does it you know what does the synthesis tool generate if you write a statement like that then they are sometime at loss even with some very trivial silly stuff. So wherever you can bring clarity by making things simple you should make it simple then use all the EFKs and you know nest it and things like that you know though we are learning about it wherever things can be made simple elegant you should do it. If the same thing is written as a concurrent statement instead of this if you are writing it outside here we are combining both next state logic and output logic together but if it is outside then you can write like this detect is 1 when present state equal to C and dean equal to 1 L0 okay. So you can write like that and here to write with select is difficult because you have 2 inputs if you are kind of adamant then you can do that what you can do is that you have to kind of group present state and the dean together into a temporary signal then you say with that signal select and put this value and so on okay. But with again it is tough with an enumerated data type because here we are using some kind of you know symbolic assignment and here it is a numerical value and though ultimately it will all be converted to standard logic vector and so on it is difficult at least to do the with select so in no harm because you are specifying both the mutually exclusive condition so there won't be any priority and this will result in a symbol logic. Then comes the synchronous reset along with when you write the next state logic and output logic together if it is alone next state logic alone there would be problem if when you combine you can make a mistake in the sense that you say if reset is 1 then you say next state gets a because that is what you want and you forget all about the outputs you say else and case present state is and you say when h0 you write the outputs there could be 10 outputs and all the transition and so on okay. But mind you there is as far as if is concerned there is one choice here and the kind of mutually exclusive choice here underneath the case come there the output is specified and here it is not specified so you get an implied latch for the reset is equal to 1 it is dangerous. So we have to say output is some value so don't care is one kind of because this say when the reset is getting kind of a certain for that duration so you can even make it inactive you don't have to say don't care you can make it the inactive value to be very sure that during when reset is 1 you don't get any nasty surprises but it is improbable. So that is one way of sorting this out another way of sorting it out is that write the if just for this and you say end if okay and write the case separate okay separate it out. So if reset is 1 then exit is a end if because we are not combining it there is no else here so like that you do and do the case present state is as I said I don't prefer this because there is this looks as if there is no else kind of thing so it could be problematic. So don't write like that you better to write like this and we also said normally if you don't specify anything like you just leave the code like this and then the tools will assign a simple kind of encoding mostly sequential encoding like this will be 0, 1, 2 and 3 okay. And if you want to kind of for whatever reason and we are going to see what reasons you could there could be to change this assignment but then if you want it you can use the kind of predefined attributes of the VHDL to control that that is called state encoding sequential gray 101, 1010 and this I am showing what was supported in the integrated you know system environment of the silings ISE or ICE okay. But I have seen that the attribute in the recent tool like the Vivado of the silings this attribute is changed so please check which tool you are using and refer to the vendor manual for the appropriate attribute but more or less the maybe some name changes but more or less the syntax is same. So here the syntax is saying attribute state encoding of whatever state you have given the name for that enumerated data type so type is gray or sequential 101, 1010 and we will see what is 101 SRA said what is it and then you get what the encoding defined by this but if you want a very specific encoding you can use attribute enum encoding of state type then you can literally say what is the encoding okay. But if that is not possible you could instead of you know you can for go the kind of enumerated data type and you can kind of hard code the present state and next state into vectors standard logic vectors and you can define constants so that you can you do not need to change like if there is a change in the state diagram then if you write numerical values in the VHDL code you have to go and change everywhere it is error prone. So you can declare define constant for each state with the proper state assignment whatever is assignment then you can implement that code then if there is a change need to be done it need to be changed only in one place you can add more state you can change the state assignment you can remove the state and so on in one place okay. Similarly the code also if you add and delete you need to change in the VHDL code but minor changes in the state assignment you do not need to change anything. And I also said about FSM editors there are graphical tools which allows you to draw the state diagram and which will create the equivalent the code VHDL or verilog there is no magic in it because it is one to one and it as you draw it as you put various elements it knows the moment you put a bubble it knows it is a state and arrow it is a transition so that is kept track and ultimately in some data structure and ultimately the some template codes are generated it is not very difficult as I said if you are I mean it can be done very easily only you need to be good in programming. So that is what we have you know discussed in the last lecture I have gone through this so that again that gets into your mind properly now we will continue with we have actually in the earlier lectures we have looked at certain issues with the finite state machine. If you remember we have looked at how to do the state diagram optimisation okay what is the basic idea what are the equivalent state and which are redundant how to detect that from the next state logic and output logic and so on. And we have also looked at the output races when there is a kind of multiple flip-flops state change state at the same time owing to the difference in propagation delay there could be transitory state and if these states produce output that could create problem in the circuit so how to handle that and we have looked at the gray coding output registering and we mentioned about the VHDL coding for that then we looked at the transition table if we choose the various type of flip-flops basically D type, T type and JK type of flip-flops and we have kind of discussed what are the maybe the advantage disadvantage and so on. So let us continue with the state assignment okay so let us take that part today so remember that you have the state machine where the next state logic output logic is there and we have the state sorry about this this should come here this cube. So we say the state machine is going through different states and when we design we say state A, state B, state C, state D but before proceeding with the next state table and output table we have to assign some numerical value to it okay. Now we are going to see whether that affect the question is that how what is the effect of state assignment on the next state logic okay say or output logic say the question is that if you do the assignment in a particular way can the area required for implementation of this can be minimal okay. Suppose there are 20 ways of doing the state assignment in at least in one of them or multiple of them the area is half of the maximum okay then it is better to choose that particular state assignment okay and that is natural because at least for the next state logic the next state is a function of the present state and the input and this is a combinational logic and we so you imagine the next state table you have inputs you have the present state you have the next state and we are trying to form equations of the various D2, D1, D0 in terms of the Q2, Q1, Q0 and the inputs so you and you know you can imagine if you are familiar with the Carnot map you go to Carnot map you try to group the min terms. So our question is that if you do the assignment in a particular way you can group it such that the redundancy can be removed and this become minimal similarly here because the output is decode of the present state and the input and if you do the assignment in such a way then whether this logic can be minimized or there is an assignment such that both can be minimized there is a very great saving in area. So if the area is reduced many a times the interconnecting wire length can be reduced the delay will be less the power dissipation will be less. So in the digital VLSI and FPGA and all that it is very wise to kind of optimize area or minimize area that will result in lot of you know advantage with respect to the power with respect to the timing and so on. So that is what we are going to look so at this point it looks like say you work out all possible assignment and find out the area which is minimal ok that is what we are going to look at it whether that is a possible thing. So that is the idea of the state assignment. So take this case the number of states are S ok suppose we have say 5 states then the number of flip flops for the binary encoding is the logarithm of S to the base 2 and normally you take the ceiling because this could be a fraction say in the case of 5 if you say log 2 it will be some 2 point something some decimal number. So we need to use take the ceiling which is 3 then we will end up using 3 flip flops ok. So now the question come is that we are trying to kind of do all possible assignment that is the that is what we have decided ok. Let us do all possible assignment. So what are the number of possible ways to do the assignment say we have S states we have n flip flops ok. Let us assign a variable to it instead of putting this in the expression log S to the base 2 is n the ceiling of it that is n. So how many possible ways you can do the state assignment in terms of n and S first thing to kind of decide is that whether in all these kind of counting problems you should be very clear whether it is a permutation or a combination. So every time if you have confusion like for a like for those who are familiar it is one shot ok. If you struggle with it the best thing to take an example is take an example of suppose you have say 4 states possible states like 0, 1, 2, 3 you have 2 sorry 4 possible states and like 2 flip flops for possible state and 2 real states S0 and S1. So then you know that the first state S0 can get any of the 4. So there are 4 possibilities ok and if you assign for possibility one of the 4 possibilities then when it comes to the next one you have only 3 choices ok. So it is a 4 into 3 so it is a permutation because each assignment is unique it is not a combination like S0 getting 0 and S1 getting 1 is different from S0 getting 1 and S0 getting 0. So that alone should clarify the position. So basically if you look at the number of possible ways to do the state assigned with this permutation of 2 raise to n because for n flip flop there are 2 raise to n kind of possible states and S is the real number of states. So P2 raise to n, S okay and let us take an example there is a state machine with 17 states and not I am it is a real life case there could be state machine with 17 states. So then n is 5 ok you will accuse me of choosing something close to the 16 but in real life it can be strange and let us find out the possible ways of doing the state assignment the permutation of 2 raise to n. So that is 2 raise to n is 32, 2 raise to 5 is 32 state is 17 so that is 32 factorial divided by 32-17 factorial. So you have some like P nr then it is n factorial by n-r factorial. So 32 factorial by 32-17 so it is essentially 32 into 31 into all the way into 16 ok and if you look at this number it is some 2.5 some decimal number into 10 raise to 44 it is a huge, huge, huge possibilities you know this should that is why I put this you know. If you try to do all kinds of all possible assignment and try to minimize area it is an interactable problem it is not going to be solved in a kind of deterministic time period it is a for the advantage we get the amount of computation we have to go through is tremendous. So this is not possible like this is mind boggling so this huge number. So this should tell you that you should not try to attempt such a thing ok of course in a simple case maybe there are 4 possible state and 3 assignment you have to make it is possible but then when the numbers are even it looks very small you end up with this because of this kind of you know the exponential way it grows. So the question is that we cannot very systematically go and solve it but our aim is that somehow minimize the next state by doing a state assignment ok or by doing a state assignment minimize the output logic. So trying all possible kind of assignment and finding out the minimal is not computationally viable solution. So then in such cases when things you cannot go very kind of you know go through all the cases and find an optimal solution we try some kind of sensible kind of rules which is called heuristic that we know that if you this rule make some sense that like if you from there is a basic principle which tells you that if you do this probably there is could be a reduction in area and we do that we may not get the absolute minimum but we can be close to the minimum or we can do better than a random kind of assignment or a sequential assignment. So we call that heuristic so since we have this systematic method does not give you any solution let us try some heuristic. So that is what we are going to do it and we will concentrate on the next state logic minimization. So the question is that what look for insight ok we want to come out with some sensible rule to apply for the next state logic optimization what do we look for insight ok. Naturally the next state logic is specified in the next state table so that is where we should look ok. So we should look in the next state table and now in the next state table you know it is composed of input present state sorry present state and next state and next state is are for a D flip flop some D2, D1, D0 and if you remember your Karnoff map for D2 we form min terms in terms of the input and the present state and then you put it in the Karnoff map and try to group them ok you can group them only if they are adjacent ok. So that is what that is that tells you some rule saying that if you play with the logical adjacency of the states that might give you an advantage in while grouping you know while grouping and applying basically applying the logical adjacency theorem. If you remember the adjacency theorem say that AB bar or AB is nothing but A into B or B bar which is nothing but A ok that is what we do in logical adjacency and that is I am talking about one variable but that can be applied to any power of 2 like you can apply to 2 tables then the 4 states are there it can be possible assignment then it can be combined to remove the 2 literals in a min terms. So that is what I mean so aim would be to look for the same next state since these state bits are output of logic and that is what we want to minimize. So we would like like you look for the same next state you know we are in a next state table we have input present state and the next state and we are trying to optimize the implementation of the next state. So look for the same next state bits suppose you are looking at D2 look D2 wherever D2 is 1 you know or the D2 D1 sorry the Q2 Q1 Q0 wherever there is next state you know kind of identical then you can make things adjacent. And for this we would like the min terms adjacent min term is considering of input condition and the present state ok. So the best bet will be that we are playing we have only choice in the state assignment present state. So we are playing with symbolic state and we are assigning it input condition we have no control ok. So it will be good to assume that if for the same next state if there are same input condition you make the present state logically adjacent then when you group it some literals will be thrown off from the min terms. So we will let us look at the same next state with same input condition and make the present state adjacent such that while grouping bits are removed ok that is the basic idea and this can be done in powers of 2 ok. So that is what I am going to show suppose you have two state and I have already learned the assignment but say this is Si this is Sj and it is transiting to the same sk 101. So the rule is that for some two symbolic state for the same input condition they transit to the same next state what you do is that you make these two states Si and Si logically adjacent ok. So this is 010, 011 it is made adjacent then when you like you group it together in when you apply the adjacency theorem you see that everything else is same but this is differing so this get knocked off ok. So this can be extended to powers of 2 say you have a 101 here another 101 here all the input conditions are same and hopefully this is like you know all 00, 001 then you can combine all the 4 and Q1 and Q0 is removed from the equation of D2 and you know D0 and all that you know that is the idea of the heuristics we can apply to the next state logic minimization. So under the same input condition if the state Si and Si transit to same next state sk make assignment such that the state Si and Si are logically adjacent and this is applicable to more than two states ok. And you can say that you know it is even if you can catch on one bit it is like you say here you look that even if in one bit suppose this is you can get a solution across a bit even for this D2 alone if you make it adjacent that is useful because at least for that there will be reduction in the next state logic for the D2 ok. That is what I have written here that state Si and Si may transit to different next state under different condition but if both transit to just one next state it is good enough to make them you know adjacent ok. So like if you can Si and Si may transit to different kind of next state at different condition but sk sl and all that. But even for one sk if you can make it adjacent it is useful. So now you get like the same heuristics can be applied to the output logic. So we are almost kind of you can straight away tell the rule the heuristic that you have two present state say let us take the more kind of output. Then the outputs are same then you just make them adjacent like you have Si and Si produces the same output make them logically adjacent so that when we group one thing get knocked off. And similarly you have four states adjacent then you make all the four logically adjacent saying that 1 1 1 1 0 1 1 0 0 0 1 so that two literals get knocked off the midterm. And if it is a mille kind of output then you have to combine the inputs you have to make sure that these are logically adjacent for the same kind of input condition that you have to keep in mind. So that is what is stated here you know under the same input condition that is for mille type if it is not mille you can remove this if state Si and Si produces same output make the state assignments such that the state Si and Si are logically adjacent ok. And it is applicable to more than two states by powers of 2 there is no point in making I mean you cannot make three logically adjacent you have to make say after two the thing you have to try is the 4, 8 and so on. And state Si and Si may produce different output under different input condition but if both produces even one output same it is good enough to make them adjacent as equation for that output get minimized. What I am saying is that you may not get a chance suppose you do not get a chance to make kind of all like such a pattern for two states you can look at the subset of these output to do that. I do not know whether the tools do it sometime in a simple state machine may not be worth to try that. I am not sure whether the which synthesis tool try it may be at least the maybe the some advance synthesis tool like Simplify Pro may try it I do not know about the reason the silings XST synthesis tool or the synthesis tool of the Vivado I have not tried it if I try it I will maybe in the later lectures I will tell you. Now let us come to this kind of issue. So, what we have discussed is the state assignment to reduce the area and we have found that for you know to evaluate all possible scenarios state assignment and come out with a minimal area is an interactable problem we have seen the huge computation type required. So, then we have come out with some heuristics which is based on some sensible kind of basics you know basics of minimization. So, it should work okay only thing is that to try and do the next state logic minimization and output logic minimization together maybe contradicting like that you try out the heuristic for next state logic minimization and you come back and try to do again for output logic both may not work together you know that is one problem with that heuristic if you are lucky it works together. So, at least you can try one thing if you find the next state logic area is much you know larger than the output logic area then you can try the heuristics for the next state logic than the output logic. But we are not sure whether we can do it together it could be contradicting the heuristics could be contradicting it may not reap the benefits as you think. So, let us come to the next issue which is something to do with the fault tolerance of the state machine. So, this is about the new state suppose we have the number of states as S okay then we know the number of flip flops is N which is log S to the base 2 the ceiling of that okay. So, there could be a new state because this the fact that you end up with a fraction and take ceiling it says that there could be a new state okay like here. So, the new state the all possible assignments the states are 2 raised to N because n flip flops are there. So, minus S is the unused state. So, if you have states number of states are 8 then N is not a fraction if you take just the log then N is 3. So, in that case 2 raised to 3 minus 8 is 0 but if it is S is 5. So, that is the case here N is 3 then the unused states are 2 raised to 3 minus 5 equal to 3 okay. So, the question is that what to do with that okay. See here I am showing an example of 5 state this 5 states. So, we have 3 unused states and assume that we have done a state assignment like a sequential state assignment a very simple state diagram and mind you this could be like in most cases there could be simple state diagram like that only thing is that there could be kind of self loops here that could be the only difference from a practical state diagram. So, let us I am not showing all the input transition but assume something like this and you have states going through 0, 1, 2, 3 and 4 but 5 are not used say 5, 6, 7 is not used okay and assume that we have not taken we have not specified this okay. We have kind of told the tool to treat it as kind of do not care or something like that and what happens the state machine is after all some 3 flip-flops okay and suppose our the circuit FPGA or the chip we are designing is in a noisy environment okay. It can be some kind of radiated EMI electromagnetic interference or conducted EMI you know that the noise conduct through the supply lines through the ground and there was some noisy equipment connected to the same power supply and some noise gets picked up either radiated or conducted and this suppose this flip-flop was in say assume that it is in 001 okay. So, Q2 is 0, Q1 is 0, Q0 is 1. Suppose the Q2 has flipped from 0 to 1 okay it was in this state and suddenly it is flipped this Q2 has flipped from 0 to 1 then the state machine gets into this state 101 okay. Now that then what happens the question is what happens okay. Suppose we have not taken care we have not explicitly taken care of that in the design what can happen okay. So, that what all can happen I mean that is what the first thing let us forget about all the technical reasoning what all can happen you just as a kind of a creative or what all possibilities are there like you can say yes it gets in there okay 101 and in the next clock it comes back here fine then it is very good it has gone there and it has come back then it continues okay. Or you can say instead of coming back here it comes back here that could be dangerous depending on the application because you are doing something very sequentially here suddenly it skip these two steps and go there it can be very dangerous depending on the application. Now you can imagine this is controlling suppose the seed machine is controlling the radiation of a patient and this is you know happened something initialization is happening this is the radiation state and with improper initialization it goes there what was 5 minutes is becoming 15 minutes then it is too dangerous you know. So, it depends on the application maybe in a simple thing like a vending machine you ask for the for a soft drink and a potato chips come out it may not matter the good for the customer little loss for the vendor but may not nothing like threatening happens but then it depends on the application. So, one possibility is that it can go there and gets come back somewhere here and at least for us probably it looks safe than you know getting it stuck okay that is another possibility you know you get it by noise it goes there and it stays there like again the clock comes but somehow it stays there. Now we will see what are the chances of it staying there but suppose it stays there then it is bad okay. So, if nothing happens it is okay but if something happens with the data path then it is dangerous okay. Another possibility is that it may loop through some or all of the unused state okay maybe like after 10 it gets into 101 it comes 111 it comes to 101 and loop or loop through this you know whatever way okay it cycles through some or all of the unused state. Now assume that this unused state produce some output okay some random output we had some say phi output arbitrarily it produces some output then it can be extremely dangerous okay. So that is the issue we are looking at it the fault tolerance if there are unused state in the state diagram or state machine and if you have not designed properly and by noise or by some chance it gets into the unused state it can come back to arbitrary state in the state diagram it can get stuck there it can loop through and if that states produce random output if you have not taken care then it can be extremely dangerous. So that is what is stated here what happens if FSM get into the state could get stuck there it could loop through some or all of unused state it could get back to a valid or used state okay get back to some of the state in the state diagram and if that state produce some random output then dangerous so on what conditions above can happen okay. So we would like to look at in which scenario kind of it gets stuck there I mean if you can understand that maybe it will at least it is better than you know thinking like you have such a problem and somehow bring it back to some kind of reasonable state. But how like in what conditions it goes there and gets stuck on what condition it get could loop through some of the unused state let us at least for an academic curiosity let us look at it from the basic principle okay. Now for that to happen so assume that we have done the next state logic coding here like this you have process present state and various input I1, I2, like that and you say begin and you say k is present state is and you say when a 0, s1 we have 5 states so you go all the way to when s4 but there is s5 and s6 and s7 and we do not specify that say we say when others okay combining all s5, s6, s7 and all possible kind of states for the simulation you know using the standard logic other cases then you say next state is don't care we are hoping that if you say don't care the next state area is minimized you know because we are not explicitly specifying that mean for these s4, s5, s6 you can read the next state as 1 or 0 and we are hoping that some minimization happen with the proper assignment and the area get minimized that is why we say next state is don't care. And that also shows the use of that particular don't care because when we discuss standard U logic and standard logic we said there is something called don't care and we have not seen it being used but this is the way it is used and we are hoping that it gets reduced area. So let us look at one condition okay one possible assignment the tool makes okay. So there you see this is a valid state 0, 0, 0 then 0, 0, 1 and there are a lot of entries up to this ellipses continuity like 1, 0, 0 okay which is the kind of s0 to s4 5 valid states and suppose this is an kind of unused state which is 1, 0, 1 I am showing with a different color and we say the input condition is don't care okay we don't care and we said the next state is also the don't care okay. Assume the synthesis tool for optimization purposes treated this as 1, this as 0, this as 1 okay that means if such a thing happens by we have written the code like that and this is the state this is the kind of assignment the tool does for optimization. Then you see what happens by mistake the present state become 1, 0, 1 and the next state decoded is 1, 0, 1 itself from the current present state irrespective of the input the next state decoded is 1, 0, 1 itself. So the moment it gets in there the next clock it transit to the same 1, 0, 1 then it loops through that and we have not even talked about the output we don't know because if you in the output table if you write 1, 0, 1 and say don't care then the same thing will happen the tool will pick assign someone some zeros and all that and then it will produce some random output which can be extremely dangerous to the application okay. So that is how this getting stuck happens and now you can imagine how the loop through can happen okay that is what is shown in the next slide. So we have the valid state 0, 2, 4, S0 to S4 and we write all the valid kind of state diagrams so everything happens but here for S5, S6 and S7 we said it is all down care okay that is what we have said. Now if the tool do this kind of assignment for whatever reason for optimization say 1, 0, 1, 1, 1 and 1, 0, 1 then what happens you see that if it gets into 1, 0, 1 the respective of the input condition the next state is 1, 1, 0 if it get into 1, 1, 0 then the next state is 1, 1, 1 and if it is 1, 1, 1 it is 1, 0, 1 so that is back here. So it loops 1, 0, 1, 1, 1, 1, 1, 1, 0, 1 okay. Now in this case I have shown all the three it can loop through the part of the state suppose here it was 1, 1, 0 and the 1, 1, 0 comes here it is back to kind of like 1, 0, 1 become 1, 1, 0 and for 1, 1, 0 it is 1, 0, 1 then it loops through the two states okay. So this is quite dangerous and as I said we are not sure what outputs are produced by this then again the don't case and all apply in the output logic table. So it is wise as far as fault tolerance is concerned to bring it back okay. Now when you say bring it back we have to bring it back to some state some valid state okay definitely valid state but in this picture I am showing it to bring it back to the initial state okay but we can only state that bring it back to a safe state okay. So that is something which you have to keep in mind we have to bring it back to some safe state and in most cases maybe the starting state is good enough suppose you take an example of a multiplication then suppose something goes wrong half way through the multiplication then it has gone to this unused state nothing happens if the best thing is to bring it to the ready for the next multiplication maybe this result is not corrupted but at least the next one happens properly but that need not be true for all kind of cases like you have a state machine you know kind of controlling something complex and which takes long time and it has gone through half way and you just bring it to the original state may not be a good idea. So maybe in the next lecture we will see how to code for this and discuss kind of scenario little more bring little more clarity to it. So the last thing we have discussed is how to handle the unused state because if the state machine get into unused state depending on how you have coded it can get stuck there or loop through some unused state or it can come back to arbitrary state which could be dangerous. So you should bring it back to some kind of safe state at least for the time being let us kind of decide on that and then we will see maybe more little more detail about that with regard to some applications. And we will continue in the next lecture with the other issues of the state machine we will try to complete that. So please go back otherwise try to grasp this concept from the basics like I have shown some minimization if you are not kind of forgotten the minimization please go back and look at it. So though the basics are simple sometime knowing the simple thing connecting it can kind of reap you will get lot of benefit out of that than getting stuck with some kind of high level language and try to write some if then and case with rhyme with no particular grasp and understanding. So that is what I want to say so I wish you all the best and thank you.