 This is Vishwana Chavan, Assistant Professor, Department of Computer Science and Engineering, Walton Institute of Technology, SolarPool. Now I am here to explain the super scalar pipeline design. Now at the end of this session, the students will be able to compare the parameters of different pipeline processors. So if we observe this table, now we will get the idea about the different parameters which are considered while designing the pipeline processors. So this is the scalar based machine of having k pipeline stages. Next one, super scalar machine which is of having degree m. Next super pipeline machine of degree n and the fourth one which is super pipeline super scalar machine of degree m, n. Now we will see all these four with respect to different parameters. First one, the machine pipeline cycle. So which is base cycle one in case of scalar base machine and here also it is one and in case of super scalar super pipeline machine which is of having degree n which is here it is one by n and here also it is one by n. The next point which is instruction issue rate. So that is one here. Here it is m. This one indicates that it issues one instruction per clock cycle and here it is m because it is having degree m. This is one. This is also m. So coming to next parameter instruction issue latency. So latency will remain one here in first two case and next it is one by n. Moving to next parameter, simple operational latency one and one in first two case. Next in third case it is one. So which is normally one into one by n which will lead one itself and this is also one. Next coming to ILP instruction level parallelism to fully utilize the pipeline which is one. Here it is m, next n and here it is m into n. So these are the different parameters. Now we will focus on the super scalar pipeline structure and data dependence. So first we will see the super scalar pipeline structure, how it looks and how it works. So this is a dual pipeline super scalar processor. So here we will find the four different stages like fetch stage, decode, execute and write back. And from this end the iCatch instruction catch which will fed the input to first stage which is fetch f1, f2, f3. Then after fetching the data from instruction catch it will forward to its next stage which is decoding stage. So respective fetch stage will forward to its next respective decode stage. Here decoding of the given instruction takes place. And after this the next stage is about execution. So here we will find the different operations like multiplication, adder, logic operations and load operation. So multiplication this unit is having three different units like m1, m2, m3. So multiplier is having three pipeline stages and adder is having two pipeline stages a1 and a2 and a logical one stage and load one stage. So all these stages they are working simultaneously because it is a pipeline. And the fourth stage which is stored or we call it as a write back. So which is having two stages s1 and s2. So which is going to receive the data from the execution stage. So each execution stage of respective instruction they will forward to either s1 or s2. So this is how the structure of superscalar processor and the look ahead window. So these F3 and D3 these two columns they see whether it is depending or not which is based on instruction dependency. So and hence it is called look ahead window. So this is the structure of superscalar processor. Now we will focus with one example. So this is a sample program and its dependency will be analyzed with the help of graph. So the instruction i1 is load r1 comma a. So here the data present in memory location a will be loaded into r1. The next instruction add r2 comma r1. So here the content of register r1 is added with register r2 and the result is stored in r2 itself. The next third instruction which is add r3 comma r4. Here the content of register r4 is added with the content of register r3 and result will be stored in r3 itself. Next fourth instruction mul r4 comma r5. Here the content of register r4 and r5 are multiplied and result is stored in r4. Next the compare r6. So it is going to compare with the value previous value r4 and result is stored in r6. Next i6 instruction mul multiplication between the content of register r6 and r7 is going to take place and the result will be stored in r6. So these are the six instructions they are working in this way. Now we will focus on the dependency, on the dependency. So if we observe the dependency say for example, first and second instruction. So here the content of memory location a will be loaded into r1 and this data is supposed to be input for next instruction. So this i2 is depending on i1 until and unless it writes into r1 it can't move ahead or else it will take wrong value. So it is depending on i1, i2 depending on i1 and hence this kind of dependency is called flow dependence. And if you observe another dependency here see here the instruction i3 which is add r3 comma r4 and next instruction which is i4 multiplication between r4 and r5. So if you observe this now it is depending. So your i4 is depending on i3 say if r3 content of r3 is supposed to add with r3 and result will be stored in r3. But here it is making use of this content for multiplication for multiplication. Here if we multiply this r4 into r5 now this data is supposed to read from r4. So this is how we say that it is depending on i3. This type of dependency is called anti-dependence. If it writes the multiplication result here before this then it will take wrong result. So these type of dependency is called anti-dependence. So moving to next which is i6 is depending on i4. Now here it is comparing after this it is going to multiply the result of r6 with r7. So here the flow is there flow dependency is there as well as the output dependency is there. So it cannot go ahead until and unless the output of r6 is available for multiplication. So output dependence and flow dependence and this type of dependency is called flow and output dependence. So all these three types of dependencies like flow dependence, anti-dependence and flow and output dependence they are shown in the diagram. We will see with a diagram. So before that now you answer for this question mention the four processing stages of superscalar pipeline. So pause this video and write the answer. I hope you answered the answer is fetch, decode, execute and store which is also called write back. Now this is the sample diagram which focuses on three different types of dependencies like flow dependence, how i2 depends on i1, next anti-dependence, how i4 depending on i3 and third one output dependence and also flow dependence where i6 is depending on i5. So these are the references. Thank you.