 Hello and welcome to this overview of GPDMA and LPDMA controllers embedded in the STM32U5. The STM32U5 embeds two new DMA controller modules, the General Purpose DMA or GPDMA, and the Low Power DMA or LPDMA. The GPDMA belongs to the CPU power domain and supports the Low Power Background Autonomous Mode or LPBAM in stop 0 and stop 1 modes. The LPDMA belongs to the Smart Run Domain and supports Low Power Background Autonomous Mode in stop 0, stop 1 and stop 2 modes. These DMA controllers are in charge of data movement between memory mapped locations, memory or peripherals, thus offloading the Cortex M33 core. GPDMA and LPDMA are two instances of the same IP and are therefore controlled by the same software driver. The DMA multiplexer connecting the requests generated by peripherals to the channels is integrated in the module. GPDMA and LPDMA support linked list-based programming to enable buffer chaining. In LPBAM, these DMA controllers are able to temporarily request the clock when a request is received in order to perform the transfer. Also, flexible intra-channel and inter-channel transfer chaining is supported without software intervention. LPDMA has a unique 32-bit AHB master port while the GPDMA has two independent 32-bit AHB ports. Transfers can be performed from peripheral to memory, from memory to peripheral, from memory to memory, and from peripheral to peripheral. The LPDMA and GPDMA support the LPBAM that enables autonomous transfers during sleep and stop modes. Channels are independent of each other and operate concurrently. They are arbitrated through an algorithm based on a four-grade priority policy. One reserved, highest priority queue dedicated to time-sensitive traffic. Three lower priority queues implementing a weighted round-robin allocation. This slide and the following two describe the per-channel programming features. The status information is visible to the software. This includes idle state, event flags, global masked interrupt status, FIFO level or GPDMA. The control information includes a software start enable, the capability of suspending and resuming a channel, resetting a channel, and aborting and restarting a channel, event flag clearing, interrupt masking. Some functionalities are statically configured and may be locked until the next reset. These are the security and privilege attributes, the port used to access the linked list items or LLI, the execution mode either run to completion, possibly executing chain transfers without software intervention, or link step mode that requires a software re-enable each time a new LLI has to be processed. Transfer chaining for a particular channel is performed through a linked list. Each item of the linked list is called a linked list item or LLI, which is a structure allocated in memory. The LLI has to be initialized with the values to transfer to the control registers when the chaining occurs. Each LLI execution consists of the optional link transfer that loads the next LLI and updates the control registers accordingly, the optional data transfer with a granularity called a block. For each LLI, the user has to program the source and destination address, as well as addressing modes and address offsets between bursts in 2D mode. The information related to the data transfer, block size, source and destination data width, and data handling. The GPDMA supports additional settings, number of repeated blocks for channels 12 to 15, and burst length for all channels. Regarding the GPDMA, the AHB port used to access the source and destination locations have to be chosen. The security attribute is also selectable when the channel itself is programmed to secure. Finally, the input and output signals of the DMA controller has to be configured. Peripheral request type and selection. Trigger mode and selection. Transfer complete event generation. The block diagrams of GPDMA and LPDMA are very similar. Requests and triggers are received on the left. They are used to activate channels that are then arbitrated. The transfer output control is in charge of generating the data transfer and the link transfer, which consists in loading the linked list item. The DMA controllers also have an AHB slave interface to enable an access to the global registers and to the channel registers. The DMA controller issues interrupt requests and DMA channel transfer complete events. Each transfer generated by the DMA controller is tagged with a particular privilege and security attributes, which are fully programmable. In the case of a security violation, an output of the DMA controller is connected to the Global Trust Zone controller. The DMA controller can generate a clock request output signal to the RCC whenever the device is in run, sleep, or stop mode. When the microcontroller enters debug mode with the core halted, any channel can either be individually continued or suspended. This table describes the features of the LPDMA and GPDMA controllers, highlights their differences, and also provides user guidelines. The number of channels is 4 for LPDMA, 16 for GPDMA. The two master ports of the GPDMA should be used as follows. Port 0 should be allocated for transfers to and from peripherals, because there is a direct hardware data path between this port and the APB peripherals outside the AHB matrix. Port 1 should be allocated for transfers to and from memory, which are performed through the AHB interconnect. This is a typical usage. The user is free to select the ports used to access the source location and the destination location. The LPDMA only supports single data transfer, while the GPDMA supports burst transfers. These burst transfers are performed through a per channel FIFO for queuing source and destination transfers. The depth of the FIFO is 8 bytes for channel 0 to 11, and 32 bytes for channels 12 to 15. Consequently, channels 0 to 11 should be allocated for transfers involving peripherals and channels 12 to 15 should be allocated for memory to memory transfers and transfers involving data demanding AHB peripherals. In terms of addressing mode, the LPDMA supports linear addresses, either fixed or incremented without stride. The GPDMA supports more sophisticated addressing modes, linear mode with fixed address or incremented address, with contiguous data on all channels, and 2D addressing only on channels 12 to 15. The number of requests and trigger inputs is not the same for LPDMA and GPDMA. The number of inputs is lower for the LPDMA, because it serves the peripherals belonging to the smart run domain. In addition to this presentation, you can refer to the following presentations – power management, reset and clock controller, ULP mark peripheral profile and LP BAM use case consumption, autonomous DMA and low power mode, DMA circular buffering and double buffering, DMA register file, DMA error reporting, DMA linked list, DMA input-output LLI control.