 Hello everyone, welcome to lecture on test bench for comparator. At the end of this session, students will be able to build the test bench for comparator and also able to verify the previously designed VHDL module using this test bench, right? Now before starting with the actual session, let's pause the video and think about what is a comparator circuit. If you remember in the previous video lectures, we have covered the different VHDL modules for different combinational and sequential devices, that is hardware, full adder, half adder, then comparator, multiplexer, right? So we have already studied that. So this is the comparator. This one is a two-bit comparator which is having two inputs, right, A and B or each one is of two-bit, right? And it gives you the output, which is a combined called Y as a three-bit signal. It has three bits, Y of 0, Y of 1, Y of 2, right? So depending on the inputs conditions, A, any one of this bit is going to be 1. If A equals to B in that case, A greater than B in that case and A less than B in that case, right? So now before writing the test bench, let's have a look at the VHDL code for this two-bit comparator and then we go for the test bench for two-bit comparator, right? So this is the code for a, okay, this is the two-bit comparator, right? And depending on this one, we have the, perform the table, so this is the table. So depending on the inputs, A equals to B in that case, Y of 0 bit is 1 and remaining two bits are 0. If A is greater than B in that case, Y of 1 bit is 1 and remaining two bits are 0 and A less than B in that case, Y of 2 bit is 1 and remaining two bits are 0. So these are the, you can say behavior of your comparator, this one. Now for this behavior, we are going to write the VHDL code. So we know that for every VHDL code, there are three important part. First is the library declarations. So we have to include the libraries, library IEEE and in that we are using the package that is STD logic 1164. Then second important part is your entity declaration part. In the entity declaration, you are going to write the different inputs and outputs associated with your design. Now in this case comparator, we have already saw that in previous slide, we have two inputs and one output. Two inputs which are, everyone is of two bits. So that's why it is mentioned as a vector A and B, 1 down to 0. 1 down to 0 means it is two bits. So there is another way you can write, instead of 1 down to 0, you can write 1 to 2. That is one way. Either you can write 1 down to 0 or 1 to 2. Again we have output associated with that two bit comparator which is of three bits. So that's why again Y is mentioned as a out bit vector type. So again 2 down to 0, so that gives you 2, 1, 0 that is three bits. Once we done with the entity declaration part, third important part is what architecture writing. So again, this is the architecture for this two bit comparator. We already saw the syntax of architecture and in that we have to mention the architecture keyword. Then architecture name is there of for which entity you are writing the architecture that entity name supposed to be here. Then your begin keyword you have to use that from that begin your actual architecture starts. Now here what we have written, if you observe over, this is nothing but it as per the table whatever we created in a previous slide. This is nothing but the y of 2, y of 1 and y of 0. Now in this case y of 0 equals to 1. So this 0, 0, 1 is assigned. This one is assigning operated in VHDL when you are dealing with the signals. So y of 0 is 1 and remaining two signal bits are 0. So this 0, 0 is 1 is assigned with 2 y when when a equals to b. This 0, 1, 0 means y of 1 is 1 and remaining bits are 0. 0, 1, 0 is assigned to y when a greater than b else 1, 0, 0 is assigned to y when a less than b. Once you done with the architecture writing you have to end the architecture. So end architecture right. So architecture is what gives the behavior of your system. So this, this is nothing but the behavior of your comparator right. Now if you done with the code you can verify the code with the help of simulation. There are different software available, tools available in the market to perform to write the VHDL code and to test that with the help of simulation. One I used over here is the Xilinx to write the code and I use the inbuilt simulator of that that is isin and you if you perform the simulation on that you will get the output sim thing like this right. So these are the signals a and b and output y right and these are the waveforms showing the values. So in this case a is having 0, 0 value and after that it is changed and a is having value 0, 1. Here the b is having value 0, 0 in this case and here it is having value 1, 1. So by comparing the code whenever a and b are equal the output is 0, 0, 1. So in during this case your a and b inputs are equal so it is having value 0, 0, 1. After this your a is changed to 0, 1 and your b is still 0, 0. So a is greater now in this period so that is why the output is 0, 1, 0. After this your b becomes 1, 1 and a is still 0, 1 right. So in this during this case period your b is greater than a. So that is why the output is 1, 0, 0. So this is how we can verify the VHDL design code with the help of simulation right. Now let us go for the test bench writing for the 2 bit comparator right. Again in the test bench writing 3 important parts are there one part is a library declaration another one is a entity part and third one is a architecture part. Same as the VHDL design code right. So library declaration you have to perform right 2 lines library IEEE and then which package you are using that package you have to mention right. Then entity declaration is there but here you have to write the empty entity no need to write the ports no need to write the signals in that one right. Just write the entity entity name entity entity name and end entity that is it end entity name that is it. After that you have to write the architecture right. So architecture name of for which entity you are writing that entity name is. Now here before writing begin we have to declare the components with the help of that component we are going to test our previously designed code. So component instantiation is supposed to be done. So component instantiation is done for unit which are we are testing. So we are testing for 2 bit comparator. So whatever the 2 bit comparator entity we are written previously that entity is taken as a component. So component same entity name same port declaration what we did in a previously designed code. So A is the input signal of vector type having range 1 down to 0 B is again having a vector type range 1 down to 0 and Y is the output vector type again but range is 2 down to 0 because 3 bit signal was there. Once we have done with the signals declaration you have to end the component. So end component right. Then we have to write the signals which are going to be mapped with these component signals right. So signal declaration parts are there inputs are there input signal A of type vector right 1 down to 0 initially value is assigned 0 0 right B is again 1 down to 0 right output Y bit vector 2 down to 0 right. Now once we done with the signal declaration part we have to write the component instantiation so that is why 1 constant is taken which is having value assigned to is 100 nanosecond right. After begin your actual architecture starts so whatever the written between the architecture line and begin keyword those are the declarative part right. Now here your actual architecture starts so here you have to first initiate the unit under test so component instantiation is done over here. So that syntax is what first you have to mention the name right component name component component we created in previous slide then port map you have to write keyword port map and in the bracket you have to map the signals with the component signal. So A is mapped with the A B is mapped with the B and Y is mapped with the Y. Once you done you are going to write the process now right. So process is there process begin right begin keyword you have to use after that after begin you going to write the every test conditions or whatever the inputs variations you are having because of the 2 input signal you have 4 possible cases in that each one A either having value 0 0 or 0 1 or 1 0 or 1 1 similarly B is having 0 0 or 0 1. So you have to write that much time so how to write that so first value of A is assigned with the 0 0 then B is assigned with the value 0 0 then we have waited for period period is nothing but the value 100 nanoseconds so we have waited for 100 nanoseconds right then we used assert statement. So actually what assert statement is do it checks for the Boolean condition and if the Boolean condition fails it assert the report statement. So whatever the message you mention in a report statement that message will be displayed so there are different types of report statement it may it can be noted can be warning it can be error right so here we have mentioned as a error severity error right if that condition fails in case. So what is the Boolean condition this condition here checking if Y equals to 0 0 1 when the Y of 0 bit is 1 when 2 inputs are equal A and B if that condition true it will not generate the report statement it directly go for the next condition right. So in this case A is 0 0 B is 0 0 so these two signals are equal so that is why we have mentioned Y of 0 bit 1 right. Again if A is greater we have mentioned over here Y of 1 bit is 1 and if B is greater Y of 2 bit is 1 and remaining bits are 0. So similarly we have to write the all the cases right one more case over here A is 1 1 B is 1 1 again both inputs are equal A equals to B so Y of 0 bit supposed to be 1 see we have mentioned over here and if that condition fails Boolean expression in that case we are reporting this statement right. Once we done all the condition now here for example I have mentioned two sample cases we have to write all the cases and after that we done we have to end the process right so end process is there then we have to end the architecture so end architecture so that is the end architecture. Now this is the code done test bench done for the 2 bit comparator once you done you can go for the simulation. So this is the simulation output you can verify with this when A this is the A signal this one is below that the signal is B right and below that the output signal Y right now here after that individual bitwise is shown output signal right wherever A and B are equal in that case your output is 0 0 1 so 0 0 1 all the 4 cases are shown over here right 0 0 1 1 0 0 1 right now whenever A is greater from this you can see Y of 1 bit is 1 filled with the grid previously Y of 0 bit is 1 remaining bits are 0 so that is why it is shown over here it is 0 1 0 so this is how you can verify the test bench also with the help of simulation these are the references thank you.