 Welcome to this lecture on VHDL and the course digital system design with PLDs and FPGAs. The last lecture we have seen the VHDL coding of sequential elements along with the combinational circuit then we have looked at I mean we started on how to write packages at least we did a preliminary kind of work towards it. So we will quickly run through the slides and get on to today's part. So the last class we have seen about the VHDL coding of synchronous reset in flip flop unlike asynchronous reset the synchronous reset is kind of synchronous with the clock if it is active then on the next clock the Q will become 0 and that is once the clock comes it has priority over the D if it is active then irrespective of the D this becomes 0 then if it is not active whatever on the next clock edge the D goes to Q. So naturally in asynchronous reset we have put it before this clock even clock is equal to 1 so that cannot be done so this is synchronous to the clock so everything happens with respect to the clock so this reset in the sensitivity list is not required also we write the reset within this clock even clock is equal to 1 because it is synchronous and we give priority to reset. So we write the reset first then the Q comes second so that is what is shown here process clock in this we write if reset is 1 Q is 0 else Q gets D and this shows a kind of multiplexer structure with reset as a select line when it is 1 Q is getting 0 otherwise Q is getting D. So the synthesized tool will put that multiplexer we will see that and we have also said that in a process the nestings allows us to kind of behaviorally represent the synchronous reset but in a congruent statement it is difficult so it does not make sense once again maybe the synthesis tool will support some kind of syntax which at least kind of semantically does not sound correct yes if it supports you can use it but then I suggest that as far as the flip flops and registers are concerned you go for a process in VHDL and this is what the synthesis tool make out of that code the clock goes here now when reset is a select line of 2 to 1 marks when reset is 1 0 goes here and reset is 0 then the D goes here then you get what you want we have looked at this Q gets D and R gets Q definitely Q and R will get 2 flip flops that is evident because you have an event on the clock what is the current value of D goes to Q at plus delta time current value of Q goes to R plus delta time so you get something like this which if you use a variable you will not get it you know that you should know that the variable you could write this with a variable and we will see that but if you do an immediate assignment you won't get this if you say Q colon equal to D R colon equal to Q then you will just get 1 R 1 flip flop not 2 flip flops okay and we looked at a shift register how to model a shift register so here it is an 8 bit shift register we have made it little awkward D0 goes to Q0, Q0 to Q1 and so on. And you could write a loop within that clock even clock is equal to 1 that is one way or you can view it as a kind of vector that is Q7 down to 0 or Q gets Q6 down to 0 and concatenated with D0 so both like this is the loop upon the clock Q0 get D0 and for I in 0 to 6 loop QI plus 1 is QI that means for the 0th index you get Q1 get Q0 for the 6th index you get Q7 get Q0 and but you could write like this Q which is nothing but 7 down to 0 is Q6 down to 0 and D0 in one shot you get it and that is also like I said you could show as a single flip flop with thick lines and the output is Q and the input is Q6 down to 0 and D of 0. So, that is two ways of looking at it I would prefer this any day than this this also kind of at least for a people who are not thorough with the syntax it looks as if it is some loop is written something which is consecutively executing which is true for simulator not for synthesis and we have seen a counter and this is standard logic unsigned is used so that we are using a plus here and clock reset is input 8 bit count output is a count is an output and since we cannot say count gets count plus 1 we define a signal of the same bit Q which is of 8 bit vector and in the code we will in the statement region we get we say count gets Q and write the code in terms of Q if reset is 1 Q gets others 0 otherwise upon the clock Q gets Q plus 1. So, and as I said this plus and one side is a standard logic vector other side is integer. So, this operator which is normally used for integer is used is overloaded in this particular package that is why this we use this package. So, in this code to note is the use of this particular package and the way we use signal to overcome the limitation of the output type of port. Because you define something as output then it cannot come on the you know the right hand side of an assignment because then it is treated as an input but if you declare a signal it has no limitation. So, that is kind of we overcome by this method and this is something which you should keep in mind and this is how it is synthesized which say that upon the clock Q gets Q plus 1. So, upon the clock Q will get Q plus 1 and that is how it is synthesized and we have gone one level up we have added an 8 bit input and a load signal. Again we treat it as a synchronous load when the load is high this DNS is loaded to the output and when load goes low it starts count from there. It is a synchronous load so naturally this comes in the clock tick event and clock is equal to 1 and we give priority to that over the counting. And this is the signal declaration standard logic unsigned library and here the count is assigned with Q process clock reset. If reset is 1 Q is initialized to 0 upon the clock now this is the game if load is 1 then Q gets D in else Q get Q plus 1 end if and this is the end if for the clock event end process and end architecture. And once again this shows if load is 1 Q gets something else Q get Q plus 1. So, this shows a 2 to 1 max where load is a select line when it is 1 Q get the D in when it is 0 gets Q plus 1. So, that is shown here. So, to the D because everything is synchronous the moment you write something underneath then that is synchronous which is connected to D and this represent a max when load is 1 Q gets D in that is this and load is 0 Q gets Q plus 1 you know that is how it is synthesized and synthesis tool might optimize it further depending on the target like in FPGA you may have kind of dedicated resources for this plus 1 and so on. So, that could be kind of and this could be a part of the logic resource within FPGA you may not use kind of standard resources within FPGA that is what I mean and when we get to the FPGA we will understand it better. And this is a coding scenario topmost code will be normally in a complex case will be the structural code made of components and each of the component could be further structural code depending on the complexity. But when it comes to the last level normally level 2 level 3 this particular component when it is reduced to a reasonable level will be composed of some concurrent statement processes procedures and things like that that is how the coding goes and the topic we have started was this how to put a component in a package and put that in a library ok that is what we have seen. The example we have taken was a flip flop and the top level entity which use this as a component is a double stage synchronizer or a two stage shift register whatever you would like to call. So, the structure is very simple the clock is called as clock which is connected together input goes to the D of the first flip flop the Q is internal signal which is connected to the D of the second flip flop and the second flip flop output is the SOP. So, we have seen how normally we write it the library the package entity D and clock are the input Q is the output and this is the behavioural code the process clock begin if clock event clock is equal to 1 Q gets D end if end process and so on. Now we are going to look at the code this particular code so we have the library entity these are the input S clock is the input SOP is the output. So, as here input S clock is the input SOP is the output we need a component called data flip flop we need an internal signal ok. So, that is declared here in the architecture declaration region we have the component declaration with the D clock and Q we have a signal declaration and the begin in the statement region we have instantiated this data flip flop twice with input S clock and internal one then that is connected to the next input S clock and SOP the game is over. Now, what we are going to do is we are going to write here we have assumed that this particular thing the component and the top level code is in one file or in one project. But we are now what we are going to do is that we are going to write this in a package and put it in a library and then we are going to use that library and package to do this kind of instantiation ok. So, one thing when we put something in a package this part the component declaration will go along with the package than in the top level entity ok. You would have seen that in a when you write a library you know functions in a library in C code you have a function prototype which is specified which goes in the header file ok. So, then you say hash include the header file and then that comes at the beginning of the code then all the data type is verified something similar happens here ok. We move this component along with the package and we are going to say use that package and automatically that comes there and the compiler can check the data type when you instantiate that is a game. So, let us look at the how to write the package we are going to write this component in a package and put it into a library and so before that a few word about the library and packages. The hierarchy of library is like this you could have multiple libraries and each library can have multiple packages and each packages can have within it components, functions, procedures and data types. All these can be in a package ok and there can be multiple package and mind you there are predefined libraries that means we are going to not to declare that that is called STD library and work library. STD library is a library which contains all the basic declarations and definitions of the VHDL that means it contains a packages which declare the bit, the boolean, the bit vector, the operators like plus, minus, relational operators, logical operators with regard to bit and boolean. All that is in a package called standard and that standard package is in the standard library and the work library is when you compile something, when you work on a design you have written some entity and architecture and you are trying to synthesize it, simulate it. So during that process that entity and architecture is kind of compiled into this particular work library and there are two packages in this standard library one is called standard and which contains all the standard data types, operators, functions and all that and it also has another package called TaxiO which basically has the all file declarations which can be used for test bench and writing something to the screen and things like that. And now mind you these things are implicitly declared you do not have to declare it when you write a code. You do not have to say library STD, work which is already understood which is implicit you do not have to say. Similarly you do not have to say use std.standard.all because that is also implicit but what is not implicit is this TaxiO package. So if you want to use TaxiO package you have to use like you have to say use std.TaxiO.all so that is a brief about the various libraries and packages, standard libraries, standard packages what is implicitly declared, what is not implicitly declared and so on. And let us now see how we can write a counter sorry not the counter the deflip flop in a package. So this is how it is written, this is the entity and the architecture of the deflip flop. So you say library declaration, package declaration, entity which we call now dff the port is dn clock is the input, q is output and we write the architecture declaration region with the process for the deflip flop. Now on top of that we write a package body which say the package some name is end that name and within that you have to write the component declaration which was earlier in the architecture declaration region of the top level entity wherever you have used this particular component but that is brought in here now. And suppose you have multiple components then you have you can write within this package body the component dff, n component, n component, counter, n counter and so on. And then you have to follow it up with all the entities like if you have a dff and a counter as component then you put a library declaration, entity for dff, architecture for dff followed with library declaration for counter, entity for counter, architecture for counter and so on. Once you do this the package coding is over. Now this particular package has to be compiled into a particular library. Now this is the syntax for writing the package but how to compile this package into a particular library depends on the tool you are working with. So you have to it depends you know sometime you work with some simulator like model sim, sometime you work with vendor tool like the Xilin's IS or ISC or Xilin's Vivado or Altaira, Quartus tool and so on okay. So how to compile a particular package into a library is tool or vendor specific. Many a times it means that you have to specify a particular library and invoke the compiler with that particular library as a target okay. So if it is a you are working with the command line then many a times you give the compiler command the file name and some option as to which library it should go to but in a kind of something with a GUI you may have to choose particular library and compile your create a project which is specific to a library and compile this file in the project to a particular library and so on. But I am not able to say anything at this moment maybe when I give a tool demo I will show you whichever tool I am using how that is to be done in a particular tool. But the essence is that you write the package and compile that into a library for the time being assume that this particular D flip flop this D flip flop is in the package is xy package and let us assume we have compiled this package this whole thing into a library called xylib okay xy underscore lib okay. Now we will see how to use that okay in the top level component this is our top level component. So we write now we have used we have put this flip flop in a package called xy package and we have put it in a library. So we are going to say library xylib IEEE use IEEE standard logic 1164.org and we say use xylib.xy package.org because that is where this particular component is and now this is the entity of the double synchronizer with input and s clock as input and so p as output. Now as I said since we say use xylib xy package.org and the component declaration is part of the xy package we do not have to declare the component okay that is already there in this particular package and we declare the signal internal signal which is signal in one is standard logic and you just instantiate the component dff this is the first one port map d input goes to d clock s clock goes to clock and int1 is the output similarly the second flip flop int1 is the input s clock is the clock and so p is output the game is done. So that is simple so the moment you put that in a component that component in a package and in a library not only you can use it anybody can use this particular package and the library particular component and they have to just say use xylib.xy package.all and they can use all the components within that particular package. So that is the meaning of this that is how you write a package now when you instantiate the same rule apply we have seen the component instantiation we have done a positional association formal to actual is associated positionally but you could say you can say here the d can be assigned with the formal to actual the clock can be assigned in particular order in any order like you can say clock is kind of associated with the s clock d is associated with the INB Q is associated with int1 as far as first component is concerned. So that is how the instantiation is done. So now let us look at the little more detail when we write a particular component in a package say when you write a code for a counter suppose you have written the counter as a 8 bit counter okay but somebody might need a 16 bit counter okay so or somebody might need a 20 bit or a 32 bit even if you think of present microprocessor or microcontroller scenario you might end up with an 8 bit counter 16 bit counter 32 bit counter and so on. So it is very awkward to write various size of counters and put it in the library but if you look at the counter code we have written everything is kind of like if you have an 8 bit counter to go to 16 bit counter there is no much change is required wherever you have set the counter size the output is say count is standard logic vectors say 7 out to 0 if you say 15 out to 0 automatically that becomes a 16 bit counter that shows that instead of kind of hard coding the width if we can say if we can specify it as a constant and somehow okay we do not specify the constant value then but when we instantiate if we can specify what is the width we require then we will get a generic counter whose size or which size is configurable okay its size can be configurable that is a basic idea and that depends in the case of counter it is very simple it may not be very simple to write generic count generic components with various parameters kind of configurable you take a FIFO you can have a configurable width may be FIFO as a width of 8 bit or a 16 bit and you can also think of a FIFO with a configurable depth like you can say a 256 entry FIFO or a 1k entry FIFO and so on. So, maybe it is worthwhile to write a configurable width and configurable that depth FIFO and similarly you can think about say you think about a dual port RAM or a multi port RAM where the width is configurable the depth is configurable number of ports are configurable all that and when it comes to that it may not be that easy to write a generic kind of code but at least in very simple cases it is very nice if you can write generic component which are configurable which has configurable sizes depth and so on okay it is up to your need and imagination that you can write the generic components. So let us look at an example of a generic counter okay counter which can be configured upon the instantiation that is our idea. So, let us look at the slide so this is how the generic so I will show the code fast then I will show the package before that. So, assume that we have a package declaration followed with a counter declaration. So the counter you see the library the packages standard logic 1164 and standard logic unsigned because we know that we are going to use Q gets Q plus 1 the see the here is the game in the entity when we declare the port say the inputs are clock and reset which is kind of in type count is output now which say standard logic vector now instead of saying that 7 down to 0 we define a constant called size okay we say size minus 1 down to 0 okay if it is 8 then it is 8 minus 1 down to 0 if it is 16 then it is 15 down to 0 and so on okay. Now we define a constant and this is nothing but a constant generic is a constant but the name given in this generic structure is this keyword generic and we open the bracket and we give the name for that particular generic size it is data type okay size colon data type and it is default value this is not the fixed value suppose at the time of instantiation if you do not specify any width then it is taken as a 4 bit counter that is the meaning of this colon equal to 4. Now we need a Q signal in the architecture declaration region the same thing applies we say instead of particular width we say Q is standard logic vector size minus 1 down to 0 count gets Q the code is same clock reset if reset is 1 Q is 0 otherwise on the clock Q gets Q plus 1 end if end process okay that is the code for a generic counter since we are putting this into a package then we write a component package header with the library and the package the 1164 package use close then we say package xy packages then whatever was in the entity like the generic and the port we write here generic and which is same as the port declaration whatever was in the entity declaration then the port declaration same component okay generic is required because you see that this data type need to be verified when we specify when we instantiate the compiler has to verify that it is integer that is why it is written here and now when you use there are two ways of using it when you exactly instantiate that in a top level component the default value is 4. So you can say like earlier you can say c1 count port map the clock that means the clock goes to the clock pin the reset goes to reset pin and the co goes to the output of the counter okay. So here you will get a counter with the default value which is 4 bit now suppose you want this to be an 8 bit counter like port is mapped from formal to actual we do a generic map formal was the constant size and the size is mapped to 8. So a label count generic map 8 and port map clock reset the co mind you in the generic you can have any number of parameters say you can think of a generic with size integer equal to 4 and then you have semicolon then you say width colon integer equal to some default value and so on. So any number of generic parameters are possible and when you map it you can say generic map then the size is mapped to something width is mapped to something with a named association you can say that. So that is shown as an example here say we are writing this is only for simulation entity nand2 that is the entity's name and this is a port declaration i1 and i2 is input, o1 is output of standard logic type and we have two generic, generic tplh that is propagation delay is of type time default value is 3 nanosecond tplh type time 2 nanosecond and somewhere in the code we are going to write o1 is i1 nand i2 after tplh plus tphl divided by 2 because this is given normally we say after 10 nanosecond after 5 nanosecond. So now this is given a proper average of the propagation delay so that is how you know that shows another example of using the generic which shows that the multiple generic can be used more than one can be used you have to map it definitely when you instantiate you have to say nand2 generic map you can say may be 5 nanosecond, 7 nanosecond and port map and things like that so exactly like this you can say. So that is how you instantiate a generic component now when you have generic in a hierarchy okay suppose we have a timer which is a generic timer suppose somebody has written a timer which is generic and the width of the timer is specified as a generic called t width okay timer width in that means you write the entity timer here you say generic t width is some integer and some width okay and we assume that after all the timer is nothing but a counter with some decoding so we assume that in the timer code this particular counter is instantiated okay and counter itself is generic you assume that the timer is generic and the counter is generic. So when you instantiate the counter in the timer generic timer the size of the counter like we had a size generic that can be because if you write that to a specific value then there is an issue because if the timer is going to be used instantiated by somebody else with a particular width so naturally that has to come down to the counter. So you can say like say count generic map t width which is nothing but the generic of the timer which instantiate this counter so essentially the generic can be kind of hierarchically passed down through the components that is meaning of it I hope that is I have made it clear because to show an example I have to write so many code so that is why this is with this much discussion I think it is most probably it is clear in your mind. So that is about basically the libraries and the packages we have seen how to put a component in a package so there is a particular package body which has to come on top of the entity and architecture and then you have to compile that into a particular library which is tool specific and once you compile then then you just say use that particular library dot the particular package dot all and you do not have to say component you do not have to do the component declaration in the architecture declaration region because that is part of the package now and then you can instantiate the components. Then we have seen how to write generic components components with a kind of generic width generic depth and so on so that when you instantiate you can specify the width or the depth or the sizes so that you do not kind of write various size components for the library you have a single generic component which when you instantiate you specify the configurable parameters then you get what you want and also we have seen that when you use it hierarchically a generic component is used in a generic top level entity the generic of the top level entity can be passed down as generic of the instantiated component so that is a lot of jugglery with the words but I think you can kind of catch the basic idea behind it. So let us move on so that kind of completes the packages but then there is one thing like when you suppose you have put a particular say counter so you have called your particular counter a counter and you have put it in a particular library okay. Now there could be somebody else might write a component called counter again and put it in some library and you use say at the beginning of the code library IEEE xylib mylib and so on and then you say use xylib.xypackage.all use mylib.mypackage.all assume that there is a component called counter in mylib and xylib and somewhere you instantiate that particular counter and depending on which package is kind of specified at the beginning that will come from that it may not be the counter that you want okay. So there has to be some way of telling the tool or the compiler saying that for this particular instantiation this particular component has to come from a particular library particular package and you can even maybe go very specific that may be that particular component as multiple architectures you may have you can say I want this particular component and a particular architecture. So the way to specify that is called configuration and there are two kind of configuration specification and configuration declaration okay. So the configuration specification basically is specified in the architecture declaration region and it binds the component instantiated in the architecture statement region to a particular library. That means basically when you say configuration specification we are going to instantiate lot of components in the architecture kind of statement region and those components can be declared in the architecture declaration region. But in the declaration region again we are going to say which library which package which is the entity architecture pair in that particular package to be used for this particular instantiation that is what is configuration specification. But when you say configuration declaration it is more than that it is a separate unit design unit that means you write a entity you write an architecture and you write a configuration for that particular entity okay. It is a separate design unit and it is hierarchical that means that you may write an entity and architecture with a configuration and a higher level entity might use this particular entity architecture pair along with the configuration and that top level entity can have its own configuration and so on okay. So this configuration declaration is a separate unit it is hierarchical it is specified at the end you know. So you have suppose you have a library and package you have an entity that entity might have multiple architectures say architecture 1, architecture 2 at the end we specify the configuration which say at least which of the architecture to be used when we particularly kind of use that in a design okay that is the basic idea of configuration. So it does two things it will bind the top level entity to one of the many architecture it has. So this configuration is going to specify which of the architecture is bind to this particular entity okay. Also not only that it will say that suppose this entity uses lot of components it will say where those components from which library which package which architecture it should be used you know which library where it comes from it specify. So it specify configuration declaration specify two things it specify which architecture to be used by the top level entity which are the components where does the components instantiated comes from is specified. So we will see both okay configuration specification and configuration declaration. We take this as an example the full adder so equations are simple A XOR B XOR C that is the sum. So we are going to instantiate two component to XOR gate AB gives S1, S1 and C in gives the sum and so here it is the carry out AB, BC, AC, AB gives S2, BC gives S3, AC gives S4 then S2, S3 gives S5, S5 and S4 gives C out. So two XOR gate, three AND gate and two OR gates okay. So let us look at the configuration specification first. So this is the library declaration we are say assuming that there are in addition to IEEE there are some HS lab, CM lab where these AND gates and OR gates and XOR gates are put and this is the full adder entity. So ABC is the input, sum and C out is the output and this is the declaration region and where we declare the components XOR2, D1, D2 is input, DZ is the output and AND2 we specify the output first then the input in the AND2 component and then the OR2 component where the inputs are first then the output is the second and we declare the internal signal like S1, S2, S3, S4, S5. So S1, S2, S3, S4, S5 is declared so that we can do the instantiation. Now when it comes to the begin this is the instantiation you say X1, X2 are the XOR gates you can see it is nicely instantiated AB S1, S1C in S sum and the AND2 is kind of reverse. So AB and S2, BC and S3, BC and S3, AC and S4 that is AND2 and OR the first OR is S2, S3, S5 that is this and S4, S5, C out that is this. Now we are going to say where this X1, X2, A1, A2, A3, O1, O2 is coming from. So mind you we have 2 XOR gates, 3 AND gates and 2 OR gates okay X1, S2, A1, 2, A3, O1 and O2 and that is specified before the begin this binding of the component to the library package or the architecture is specified before the begin. So we go back and you see after the component declaration, signal declaration we are specifying the configuration. So we say that 4 X1, X2 these are the instantiated kind of labels colon that is a entity XOR2 use entity work which is a work library dot XOR2 that means that is a entity name. We assume that there was we have written an entity called XOR2 with multiple architecture which is compiled into a work library and you see in the bracket which is say XOR behave or be which is the architecture we have used okay. So we assume XOR2 has multiple architecture. This is a particular architecture we want to use for X1 and X2. So the syntax is 4 label the entity use entity library if you have package dot package dot entity and within the bracket the architecture. Similarly say 4 A3 and 2 use entity library here there is no package it is directly compiled in library the entity architecture and you could even change the port mapping by kind of if you use some other port names in the instantiation you can change it from the formal to the actual whichever way you have used for the instantiation. So you can re do the port mapping and for all OR2 that means for all instantiation of OR2 use entity you know this particular library entity and architecture for others and do that means we are here we have used only for A3 for all other and to use the particular library entity architecture and the port map is done to change the port mapping. So that is how the specification configuration specification is done wherein the instantiated components are bind to particular library packages entity and architecture ok. So let us see the configuration declaration so which has two purposes which binds an entity to architecture. So we are assuming that this particular entity for which the configuration is written as multiple architectures and which also bind the components which is used in the architecture to a particular library. So let us look at the very simple example wherein the entity is just bind to the architecture. So there this is the syntax configuration which is a keyword a name. So here we are writing the configuration for full adder. So I have called it FA underscore con FA con of full adder is and we say end that name then that is the body of the configuration declaration and inside we say for FA underscore str. So this is the architecture which to this particular entity is binded ok for FA str n4 ok. So very simple thing we bind the entity to architecture. So this particular entity is bound to this particular architecture but assume that you have a lot of components are declared and you want to bind those components to specific library. So that can be specified within this body of like you say for FA str n4 within this you can specify as we have specified in the configuration specification. So that is shown here like configuration name of full adder is and you say for FA str n4 that is why it is that is how the entity is binded to the architecture. Now within that you can say for a1, a2, a3 and to use entity library entity architecture and so on. So all how we have done like for others or two means for all or two we do not say anything it can come from anywhere. But interestingly we say here for all x or 2 that means in our previous case you had x1, x2, 2 instantiation we say use configuration work dot x or 2 con that means for this particular entity x or 2 there is an architecture may be multiple architecture. Also in along with the entity there is a configuration called x or 2 con which binds the x or 2 entity to some architecture which binds if at all some components is used within the x or 2 that is bind to a particular library. So that is how at the beginning we said that the configuration is hierarchical. So we have a configuration for the full adder and we also have a configuration for the component used within and we just say use that particular configuration. So that is what how the configuration declaration is that. So now so the two things we have seen with the configuration is that basically configuration specification and configuration declaration. Configuration specification is specified in the architecture declaration region. So whenever you have some components instantiated in the architecture statement region this configuration declaration specify where these component labels by labels you can specify where it comes from which library which package which entity and which architecture. Okay and the configuration specification bind that particular entity to an architecture also it says if the components are instantiated where it comes from and the configuration can be hierarchical. So you could write components with configuration and go to a top level entity where this components is used and you can say at the top level entity to use that particular configuration for those components instantiated. So that is hierarchical. So that is kind of complete the library and packages we have seen how to write generic you know library packages how to put it in library how to instantiate it how to use generic packages and how to specify where these components should come from by configuration specification configuration declaration and so on. So we have little more portion left in the VHDL for a logical conclusion before we start with the controller in digital kind of state machine. So maybe we have a we will have a brief look at it and we will try to complete in the next lecture. So I just want to give various packages operators and function so that you are familiar you can use it properly. So we have seen this particular package already like you have a package called standard logic 1164 which is an IEEE package in the IEEE library and we know that the standard U logic is defined in that we have seen it. It takes 9 values Ux01, ZW, LH and dash which is down care and we have a subtype which is called standard logic which is a resolved version of standard U logic. And I briefly mentioned earlier resolved means when multiple standard U logic drives a bus this resolution function tell what is the resultant value that is the meaning of this resolved. We will see that as we go along in the VHDL and we have a standard U logic vector defined as an unconstrained array standard logic vector which is defined as a unconstrained array of standard logic. And we have in this standard logic 1164 package all the logical operators like AND, NAND or NOR, XOR, XNOR and NOT overloaded for this particular standard logic and standard logic vector okay. So you want to use that then logical operators with the standard logic then use particular library and also it has another because this only specify the logic operators but we need arithmetic operators, we need relational operators but that is not found in the 1164 library package and that is specified in this particular package like standard underscore logic underscore unsigned package it is specified. And basically it specify the standard logic and standard logic vector and you have these operators arithmetic operators you have plus minus multiplication and division you have relational operators like less than greater than equal to not equal to less than or equal to and not I mean greater than or equal to. You have shift operators now mind you that this is called SHR shift right and SHL which is shift left okay. And you can convert this many a times in the code we need to convert a standard logic vector to an integer say example is that you have some address as a standard logic vector and you are right trying to write the VHDL code for a memory or a FIFO and this the address location is an array okay. So, you specify address as a say 4 bit 1010. So, it should go to the 10th location. So, normally that is converted to an integer as a 10. So, where in this is used which is called con underscore integer and you specify the standard logic vector here you get the integer as a it returns an integer which can be used as an integer type. So, I think we will see in the next lecture all the packages various packages various operators. So, that you can use these packages to quickly design that is the basic idea. And also if you have a idea about various packages various operators it is very easy to code and very easy to be kind of keep compatibility. So, what is the kind of recommendation of what is current packages because there are some old packages which is kind of superseded by the new packages. So, it is recommended that when you design use the current packages than the old one and things like that and some packages may be used for a particular only simulation not for synthesis. So, all that we will see in the next lecture please go through the portions provided try to understand it work out small example. So, that you become thorough with the syntax and you get the idea. So, I wish you all the best and thank you.