 Welcome myself, Giridhar Jain, Assistant Professor in Electronics and Communication Engineering, Valchin Institute of Technology, Sholapur. Now today, I am going to deliver a lecture on CMOS logic, power dissipation. Now learning outcomes of this session are, at the end of this session, students will be able to explain static, dynamic and short circuit power dissipation in CMOS logic. Now content of this lecture are introduction, static power dissipation, dynamic power dissipation and short circuit power dissipation. Now introduction, power dissipation basically consists of two elements. First is static power dissipation. Now the static power dissipation is due to the leakage current drawn from the supply and second element is dynamic power dissipation which consists of switching transient currents at the time of switching and second is charging and discharging of the load capacitance. Now let us understand static power dissipation in detail. Now this is CMOS inverter which consists of PMOS and NMOS. This is input and this is output. Now when input is equal to 0, PMOS is in on state and NMOS is in off state therefore, output is equal to logic 1 means output is connected to the VDD and when input is equal to 1 then PMOS is in off state and NMOS is in on state therefore, output is equal to 0 which is connected to the ground. Now in static power dissipation we see that here only PMOS conducts and here only NMOS conduct means there is no circuit completed from VDD to the ground means we expect that the current drawn from supply to the ground under steady state is 0 means static power dissipation we expect it is to be 0 but practically the static power dissipation is not 0. Now to understand this now let us have a construction diagram of the CMOS inverter which shows. Now here this is basically this is P substrate on to P substrate there is a N well is obtained by diffusion on to N well this is P plus P plus so this is a source and this is a drain of PMOS and this is a substrate for PMOS. Now on to this P substrate directly this is N plus N plus so this is drain and this is source and middle is gate here also gate and this is a substrate so this is connected to the ground. Now drain of the two MOSFETs are connected together which is output and the gate of two MOSFETs are connected together which acts as a input. Now here between this P and N there is a diode between N and P there is a diode means whenever there is a P type semiconductor and N type semiconductor a diode is formed. Now these diodes are called as parasitic diodes means they are not manufactured they are the byproducts of the manufacturing process. Now already we have seen that only PMOS or NMOS conducts at a time. So when PMOS is conducting then current will flow from VDD then through this diode and this diode is reverse bias and it goes to the ground. After condition PMOS is in off state and NMOS is conducting means current will flow from VDD either through this diode or directly then through this diode again so this is reverse bias and NMOS is conducting so through this diode then NMOS and goes to the ground means in both the possibilities this diode is reverse bias. Now as this diode is reverse bias a reverse leakage current flows and this leakage current is responsible for a static power dissipation. Now current through diode is given by I0 is equal to Is in the bracket e raise to Qv upon kT minus 1. So here Is is a reverse saturation current Q is a electronic charge V is voltage across diode k is a Boltzmann constant and capital T is a temperature in absolute degrees Kelvin. Now a static power dissipation is leakage current multiplied by the supply voltage. So it is given by summation of 1 to N leakage current multiplied by supply voltage where N is the number of devices means static power dissipation is leakage current product of leakage current and supply voltage for N devices. Now next is dynamic power dissipation due to charging and discharging of the load capacitance. Now this figure shows a CMOS inverter with input equal to 0 and here input is equal to 1. Now when input is equal to 0 PMOS conducts and here this CL is a load capacitance. Now load capacitance is the equivalent equivalent junction capacitance of the load. So load means for example output of this CMOS inverter is given again to a input of another CMOS inverter. So again there are two that is PMOS and NMOS. So between gate and ground you will see a junction capacitance is there between gate and source. So this is equivalent capacitance of the load CL. So when input is 0 PMOS is conducting therefore a load capacitance is charging from VDD PMOS. So this is charging of the load capacitance takes place and during charging current flows through the PMOS therefore a power is dissipated across this PMOS. Similarly when input is 1 then NMOS is conducting and PMOS is in off state therefore load capacitance which was charged earlier means earlier say output is logic 1 and when input becomes 1. Now see here the load capacitance discharges through NMOS. So discharge current flows through the NMOS so there is a power dissipation across NMOS due to this discharge current means when output becomes 1 there is a charging of load capacitance through PMOS and when output is 0 there is a discharging of load capacitance through NMOS. So charging and discharging produces the dynamic power dissipation. Now this is a short circuit power dissipation. Short circuit power dissipation means this is a power dissipation at the time of switching. Now this is waveform for the input voltage and this is the waveform for a short circuit current. Now when input exceeds VTN or when input is between VTN and VDD minus VTP the short circuit current flows. So this is the waveform for short circuit current and let this is I max and this is I min. So short circuit power dissipation is given by PSC is equal to I min into VDD therefore total power dissipation is sum of static power dissipation, dynamic power dissipation and short circuit power dissipation. Now out of all this component dynamic is dominant short circuit is about 10 to 20 percent and static is very small. So this is about power dissipation of CMOS logic. These are references. Thank you very much for listening the video.