 Hello, and welcome to this presentation of the STM32U5 low power timers. It covers the main features of these ultra low power timers. The low power timer peripheral embedded in the STM32U5 microcontroller provides a 16-bit timer that is able to run even in low power modes. This is made possible thanks to a flexible clocking scheme. The low power timer peripheral provides basic general purpose timer functions. A major function of the low power timer configured in asynchronous counting mode is its ability to run even when no internal clock source is active. The low power timer's main feature is its ability to keep running even in low power mode when almost all clock sources are turned off. The low power timer has a very flexible clocking scheme. It can be clocked from on-chip clock sources, LSE, LSI, HSI16, MSIK, or APB clocks, or it can be clocked from an external clock source over the low power timer's LP TIM in one input. This later feature is used for building pulse counter applications and is a key function for metering applications like gas meters, etc. The low power timer features up to eight external trigger sources with configurable polarity. External trigger inputs feature digital filters to cancel out faulty triggers that could be raised in noisy operating environments. The low power timer can be configured to run either in continuous or one-shot mode. One-shot mode is used for generating pulse waveforms while continuous mode is used to generate PWM waveforms. Input capture and PWM functions are available in the two LP timer channels. LP timers can request DMA transfers whenever an input capture event or an update event occurs. The autonomous mode enables the LP timer to temporarily request its kernel and bus clocks when needed in order to transfer data with DMA. The low power timer is a peripheral split into two separate clock domains. The APB clock domain on the left of the figure contains the peripheral's APB interface while the kernel clock domain contains the low power timer peripheral core functions. The kernel clock domain on the right of the figure can be clocked by internal clock sources or by an external clock source through the timer's LP TIM in one input. The low power timer peripheral embeds a 16-bit counter that is fed through a power of two prescalar. The low power timer peripheral features a 16-bit auto-reload register and a 16-bit compare register that are used to set the period and duty cycle respectively for a PWM waveform signal output on the timer's LP TIM out output, steered to either LP TIM CH1 or LP TIM CH2 output, according to the PWM channel number. The low power timer features a repetition counter which allows to adjust the counter rollover. At last, the low power timer features an encoder mode function that can be used to interface with incremental quadrature encounter sensors using the peripherals LP TIM in one MUX and LP TIM in two MUX inputs to select the direction. These input signals are visible on the upper right of this figure. All timer inputs support a glitch filtering circuitry. The LP TIM CCRX and LP TIM ARR registers in conjunction with the bit fields wave from the LP TIM CFGR register and single start from the LP TIM CR register are used to control the output waveform. The output waveform is either a typical PWM signal with its period and duty cycle controlled by the LP TIM ARR and LP TIM CCRX registers respectively. Or it is a single pulse with the last output state defined by the configured waveform. If the last output state is the same as the one at the waveform's beginning, then one pulse mode is configured. Otherwise, set once mode is configured. The low power timer's output polarity is controlled through the wave, pole, bit field in the LP TIM CFGR register. By setting the polarity bit, the default state of the output is high level and the waveforms are once complemented with respect to the ones represented in the figure. The PWM mode generates a signal with a frequency determined by the value of the LP TIM ARR register and a duty cycle determined by the value of the LP TIM CCRX register. The LP TIM is able to generate PWM in edge aligned mode. Dynamic modifications of the PWM period or duty cycle can be performed by CPU or DMA accesses. The following PWM events be used to raise an interrupt request. Counter overflow, repetition counter overflow. The 8-bit repetition counter decrements set each counter overflow and triggers an interrupt when it reaches zero, which is convenient to adjust the interrupt rate. This slide describes the input capture features. Each channel can be individually configured as input capture with various signal conditioning options. The edge sensitivity is programmable and can be rising edge, falling edge, or both. An event prescalar captures of one event every two, four, or eight events as programmed in the prescalar. Spurious transitions due to noise or bounces can be removed using a programmable digital filter. Once the capture trigger is issued, the timer's counter value is transferred into the capture register and an interrupt or a DMA request can be issued. If a new capture occurs before the previous one has been read, the capture register is overwritten and an overcapture flag is set for the software to manage this condition if needed. LP timers 1-3 are autonomous and can operate in stop mode by requesting their kernel clock and their bus's APB or AHB when needed in order to transfer data by DMA. They use GPDMA or LPDMA depending on the peripheral and power mode. The APB clock is requested by the peripheral each time data must be transferred to or from the SRAM. Once the APB clock is received from the peripheral, either an interrupt or a DMA request is generated depending on the LP tim configuration. In order to offload the CPU in run mode or to avoid waking it up when in stop mode, it is possible to use LP tim DMA requests to transfer the captured values when in input capture mode or to update LP tim registers when in PWM mode. When in stop mode, the LP tim counter can be automatically started after the detection of an active edge on one of its external input triggers. When PWM mode is active while the LP timer is in autonomous mode, the LP tim can be configured to autonomously change the pulse width and or the duty cycle of output waveform at each update event without any CPU intervention. The update event or UE flag is automatically cleared when the auto reload register is written which can be performed by a DMA right. When input capture is active while the LP timer is in autonomous mode, each time a counter value is captured and available in the LP TIM CCRX register, the APB clock is requested by the peripheral and a DMA request is generated. The captured value is then transferred to the SRAM. The CCXIF flag is automatically cleared by hardware once the captured value is read by APB. It can be any bus master like CPU or DMA. To summarize, no CPU intervention from the CPU is required to re-enter the stop state in which both the kernel and the APB clocks are gated off. The low power timer features a counter reset function used to reset the zero to contents of the LP TIM CNT register. Two counter reset mechanisms are possible. The synchronous counter reset mechanism and the asynchronous counter reset mechanism. A synchronous counter reset is performed by setting the count RST bit. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of three LP TIM kernel clock cycles. When the RSTAR bit is set, an asynchronous counter reset is performed on the next APB read access to the LP TIM CNT register. The low power timer features an encoder mode function that can interface with the incremental quadrature encoder sensors using the peripherals input 1 and input 2. This mode allows handles signals from quadrature encoders used to detect the angular position of rotary elements. Encoder interface mode simply acts as an external clock with direction selection. This means that the counter just counts continuously between zero and the auto reload value programmed in the LP TIM ARR register. From the two external input signals, input 1 and input 2, a clock signal is generated to clock the LP TIM counter. The phase between these two signals determines the counting direction. Both inputs feature glitch filtering circuitry. The encounter function is similar to the one embedded in the general purpose timers. In order to use the encoder mode function, the low power timer must be running in continuous mode. One important thing to note is that only low power timers 1 and 2 embed the encoder mode function. This table lists the interrupts and DMA request sources. The capture interrupt or DMA request is generated once the counters of the counter register LP TIM CNT matches or is greater than the compare register LP TIM CCRX contents. The compare match interrupt or DMA request is generated once the contents of counter register LP TIM CNT matches or is greater than the compare register LP TIM CCRX contents. The auto reload match interrupt is raised when the counter register's contents matches the auto reload register's contents. The external trigger event interrupt is raised when a valid external trigger is detected. The auto reload register write OK. The compare register write OK. And the repetition register write OK. Interrupts are raised when the transfer of the contents of the LP TIM ARR register, the LP TIM CCRX register or the LP TIM RCR register respectively is completed from the peripheral's APB interface logic into the peripheral's core logic, which are contained in two different clock domains. These three interrupts are useful in mitigating the overhead of polling on the status or writing to these status registers when the peripheral core clock is much slower than the APB interface clock. The up and down direction change interrupts are raised when the encoder mode function is enabled and the counting direction is changed from up to down or vice versa. The counting direction of the low power timer's counter reflects the rotation direction of the quadrature sensor. The update event interrupt or DMA request is generated when the repetition counter underflows and the LP TIM counter overflows. The low power timer peripheral is active in sleep and stop power modes. The next slide indicates which LP TIMers remain functional in stop to mode. The low power timer wakes up the microcontroller from either sleep or stop modes. The STM32U5 devices embed four LP TIM peripherals. Three of them are connected to APB3, LP TIMers 1, 3 and 4, while LP TIMer 2 is connected to APB1. The clocking scheme in the RCC is also different for LP TIMers 1, 3 and 4 with respect to LP TIMer 2. Only LP TIM 1 and LP TIM 2 instances support the encoder mode. LP TIM 1, 2 and 3 implement two channels where each channel can be configured in input capture or PWM mode and therefore these timers can operate in autonomous mode. The LP TIMers 1, 2 and 3 also implement three DMA request signals, two related to input capture, one related to the update event. Wake up from stop 0 and stop 1 modes is supported by all of LP TIM instances while wake up from stop 2 is not supported by LP TIM 2. For more details, please refer to the following documentation available on our website. In addition to this presentation, you can refer to the following presentations Reset and clock controller and power management.