Shaper phase-code-manipulated radio-pulse (forward and reverse 13-position Barker code) on the FPGA. Methodical example.
Developer: Sergey G. Badlo
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In areas such as the radar, the use of complex signals like chirp or phase-sequence code-manipulated (FCM) is a classic. One typical FCM, perhaps, be called - Barker code, noted that its autocorrelation function has a minimum level of side lobes, which positively affects the results of the detection of the desired signal in noise and, of course, the accuracy of determining the coordinates of the target. Barker sequence in mathematics - is a sequence of numbers where each element is equal to +1 or -1. The code can be 2, 3, 4, 5-7-E, 11-minute and 13-positional. Today we will form the FPGA pseudo-radio based on the longest of the FCM 13-position direct Barker code: 1 1 1 1 1 0 0 1 1 0 1 0 1. How? Simple enough. Suppose we have a signal from the oscillator whose frequency is equal to the intermediate frequency processing channel (ADC transfer or without transfer of the spectrum, we will not go into details), or differs from it by a certain amount (the amount of discrete), which is expressed known Doppler effect (frequency shift ). But no matter. Each position in the sequence Barker will have a predetermined time duration (min discrete, clock cycles). Positive position value (1) will be given direct phase clock pulses from the generator, and a negative (-1) in opposition. Thus, the entire sequence will be cutting pulse clock signal and a predetermined duration. To simulate the same end radio, ie further feed it to the ADC input, enough to yield the corresponding configured FPGA hang usual resistive voltage divider and then loaded onto the coaxial cable. Divider will reduce logic levels to an acceptable level on the input channel reception and processing, and the capacitance of the coaxial is kinda anti-aliasing filter.
Structurally, the core module 'FK-BARKER' (see diagram) includes the following blocks:
1. Generator set duration positions in Barker - NTI.
2. RS-flip-flop to the D-flip-flop.
3. Delay circuit starts issuing the Barker sequence.
4. Shaper overheads on the counter and multipliers.
5. Mixer clock signal on and '2 '.
6. Shaper phase cycles (conventional inverters).
DESCRIPTION OF WORK
On arrival of the trigger pulse of positive polarity IZ snaps RS-trigger bill authorizing clock delay circuit start issuing Barker. The delay start issuing Barker performs the shift of the overheads of the trigger pulse at a predetermined interval, and implemented on a classic counter and Flip-Flop c trigger asynchronous reset. By triggering the trigger, the release shaper overheads, which forms the duration of each pulse (bit) in the overhead Income (front) clock NTI. NTI clock cycle selected based on duration of one position in the code Barker equal 834 ns, and is tied to reset to the start signal IZ for synchronicity.
Shaper overheads represents nothing other than the transducer parallel to serial. The principle of operation of this converter is very simple - for a given combination of a counter is logical multiplication given code on a predetermined signal (single bit), ie for each of the 0 ... 12 bits set corresponding to the combination of code from the counter, then all signals are added by OR. Thus, for each time at the output of adder is present "its bit" from a parallel code. The phrase "his bit" in quotes because it is actually applied to a mixer or misphased phased clock signal according to the 13-hole Barker code. To others in times outside the start and end of the output generator overheads overheads attended zero, passing resolution scheme is implemented "and" to resolve the account output macroblock DIV-SUM. Code = 00001101 13 decoder circuit for "AND" formed to reset all the slice and a counter for closure (ban) overheads, and tossed RS-trigger in the initial state before the next trigger pulse. To switch between the direct 1 1 1 1 1 0 0 1 1 0 1 0 1 and 13 reverse-positional Barker code 1 0 1 0 1 1 0 0 1 1 1 1 1 used buferniki BUFT, with the possibility of transfer to Z-state, commuting phase of the 1,3,7 and 5,9 and 11 sequence bits.
FEATURES OF REALIZATION
1. To reduce crosstalk and interference, PCB layout should be done with a single continuous layer of metallization, locking ceramic containers about supply pins. All nazadeystvovannye custom pins I/O FPGA planted inside the ground and configured as outputs.
2. All counters and triggers asynchronous.
The author assumes no liability for any damage to equipment or information as a result of unauthorized use of the project or "hands off your curves." He also makes no warranties, express or implied, regarding the correctness of results and assumes no responsibility for any direct or consequential damages resulting from its use.