 Hello, and welcome to this introduction to microphones. In this video, I'm going to cover the details of PDM microphone acquisition using the DFSDM interface on STM32. DFSDM stands for Digital Filter for Sigma Delta modulators. This peripheral is able to both acquire and convert to PCM the bit stream coming from PDM digital microphones. It implements the kind of filtering and decimation required to convert PDM to a PCM signal. It offers the great advantage of offloading the core from the computation which usually is performed by means of the PDM to PCM library. The user can do connect one or more microphones to the MCU and obtain the PCM data in a buffering memory with no software efforts. The peripheral is composed of three main parts. We have the channels which are responsible for data acquisition. Each channel can acquire data from a PDM line on a single edge of the clock, either rising or falling. Two channels can be internally connected to the same PDM line. In this way, it's possible to configure them to acquire data on both edges of the clock by using one channel to acquire the rising edge and the other to acquire on the falling edge. The second component is the filter, which is responsible for the actual conversion to PCM. Each of them applies a low pass filter and decimates the signal coming from a specific channel. The control block is responsible to generate a proper clock, and it controls the functionalities of the whole peripheral. When we set up the peripheral, we can assign a filter to the specific channel we want to convert. Depending on the STM32 part number, there can be a variable number of channels and filters. The number of microphones that can be converted in real time is equal to the number of filters. For two microphones acquisition, a single data line can be used with the microphones configured with opposite left-right pin. The clock is usually provided by the DFSDM peripheral to the microphones, but it can also come from an external source and clock both the microphones and the DFSDM using a dedicated clock input pin. In this case, two channels will be used to acquire the data on both edges of the clock, and two filters will be used to convert them to PCM. Four microphones can be acquired and converted, connected to couples of microphones to two data lines. In this case, four channels and four filters will be used. In this specific example, two clock pins are used in order to be able to switch between a low-power case in which a single microphone is acquired and clocked, and the high-performance mode where all the four microphones are used. Four main parameters must be taken into account for the DFSDM. The clock divider, the filter order, the oversampling, and the right bit shift. The DFSDM peripheral has a clock input which may come from a PLL, from the system clock, or from the peripheral clock. The internal clock divider rescales this input clock and defines the actual frequency provided to the microphones. The oversampling parameter defines the decimation ratio to be used in the conversion. The output sample rate of the PCM signal will be equal to the clock provided to the microphones divided by the decimation ratio. For further information on this concept, you can refer to the previous video of this series in which the PDM to PCM conversion is discussed in details. The filter order defines the kind of response you want to obtain on the filtered output. Increasing the order results in general in a stronger attenuation and noise rejection. Here are some examples of the frequency response depending on the filter order for a decimation ratio equal to 64. This is the response of the sync3. Here in red the response of the sync4 is added which is able to obtain better attenuation. In yellow we have the response of the sync file. The resolution of the output data depends on both the filter order and the decimation ratio. For each combination of order and decimation ratio there will be a specific maximum output value. The internal structure of the DFSDN supports up to 32 bits which cannot be exceeded. After the computation of each sample before the data is moved to the output register, a right shift of a configurable number of bits is performed. These serves mainly two purposes. The first reason is relevant to the data register, which, as you can see, can host up to 24 bits of data. If the DFSDN oversampling and sync order are configured to generate a maximum number that is more than 24 bits long, some of them must be discarded with the right bit shift before moving the data to the register. Please also note that the eight less significant bits of the register must always be discarded since they don't contain audio data. The second reason to use the right bit shift is for gain control. Being able to control the dimension of the output data basically allows tuning of the gain that is added to the microphones. Here are some useful references you can find on st.com. More videos in this video series can be found on the ST Microelectronics YouTube channel.