 Hello, and welcome to this presentation which describes the circular buffering and the double buffering supported by the LP-DMA and the GP-DMA. The DMA is used to transfer 16-bit samples acquired by ADC-4 to a buffer in SRAM containing 128 samples with minimum software intervention. In order to automatically reload the destination address register with the start address of the buffer, a linked list containing two LLIs is implemented. LLI0 provides all the required initialization while LLI1 only restores the destination address register. The CXLLR register is not updated after LLI0 so that each time the buffer is full, LLI1 restores only the destination address. Two interrupts are enabled, half transfer complete and transfer complete. Let us describe the initializations that apply to both GP-DMA and LP-DMA. In the CXCR register, interrupts are enabled and the channel is activated. In the CXTR1 register, the addressing modes are selected, fixed for the source address and incremented for the destination address. The source data and destination data widths are also selected, 16-bit half-word in both cases. In the CXTR2 register, the transfer complete event occurs when a block is transferred. The request input is selected. Here it is ADC-4 while no trigger is used. In the CX SAR register, the address of the ADC data register is programmed. In the CX DAR register, the start address of the buffer in memory is programmed. In the CXLLR register, the link is configured. Only the DAR register is reloaded. When the GP-DMA is used, the configuration can be modified to improve the performance. Instead of moving half-words to the buffer in memory, the channel FIFO collects half-words, packs them into words and writes words to the buffer. This is achieved by programming the destination data width to the word and setting the PAM field to 1x in order to enable the source data FIFO queuing and packing up the destination data width. The slide describes the automatic update of the source or destination address register when a unique circular buffer is used. As a unique buffer is used, the half-transfer complete interrupt is required to ensure that software has processed the received samples before the DMA overrides them with the new ones. The automatic restoration of the source or destination address can be performed by two different approaches. The first one corresponding to the figure on the left was described in the previous slide. The main LLI0 configures directly the linked list register of the channel. The LLI0 data structure is not in memory. Only LLI1 in memory restores the source or destination address and is the only one executed. An alternative approach is to have no data transfer described by the channel X linked list register but the LLR register pointing to the LLI1. LLI1 is the main data structure in the memory instead of being directly initialized in the register file and points to LLI2 data structure. LLI2 only restores the source or destination address and is the only one executed. If circular buffering must be executed after some other transfers over the shared DMA channel X, the second approach is required. The penultimate LLIn-1 in memory is needed to configure the first block transfer and the last LLIn restores the memory source or destination start address. The management of a ping-pong buffer pair can be preferred versus a unique circular buffer. The figure on the left describes the implementation without any first data transfer via the register file and only a link transfer for the loading of the LLI ping data structure. When the first request and possibly trigger is received, the LLI related to the ping buffer is executed. Once the buffer is full, the transfer complete interrupt is generated to inform the software that the ping buffer contains data ready to be processed. The link transfer for loading the LLI related to the pong buffer also occurs when the ping buffer is full. Once this pong buffer is fully executed, the transfer complete interrupt informs the software that the pong buffer contains data ready to be processed. The link to the LLI related to the ping buffer also occurs when the pong buffer is full. Then the same sequence repeats. The figure on the right describes a sequence in which LLI0 directly configures the DMA to execute the ping buffer and afterwards load the LLI pong buffer from memory. With the double buffer management case, when the pong buffer is full, a second LLI in memory to describe the ping transfer is always needed. In addition to this presentation, you can refer to other presentations on the GPDMA and LPDMA, DMA overview, DMA transfers hardware and software views, autonomous DMA and low power mode, DMA link list, DMA 2D addressing, DMA register file, DMA error reporting, DMA input output LLI control.