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Published on Mar 24, 2014
There are dozens of occasions where designers need to verify the sequential equivalency of two different RTL circuit descriptions. Unfortunately, simulation-based RTL equivalency checking approaches -- where the results of "golden tests" are compared to the runs with the new circuit -- assume the golden test suite exercises all functional corner cases. Of course, simulation is not exhaustive by definition so even the most carefully constructed RTL simulation regression suite will fall short at this task.
In this video Jasper's Deepa Sampathu shows how Jasper's formal Sequential Equivalency Checking (SEC) App can exhaustively and efficiently address the most common SEC use cases, including detailed highlights from two real world case studies.