 Welcome to this lecture on digital system design and the course digital system design with PLDs and FPGAs. In the last lecture we have looked at what are the features of Millie and Moore output when can we use the Millie output and then we looked at the state machine controlling the data path through clock gating and recirculating marks, its advantages, disadvantages, how is a power dissipation and a solution for it and associated VHDL coding and so on. Today we will address some more issues of the state machine when you design some things are related to kind of optimisation which sometimes the tool does not support or tool does not support to a degree where it can be kind of used. You have to check whether your tool supports otherwise you can try to implement this manually which may be little difficult in some cases but at least to be aware of these issues will be useful when you are kind of in a difficult situation. So let us run through the slides of the last lecture before we get on to today's portion. So let us move on to the slide and we have said that we have taken the example of our ADC controller here in the Moore output when the start comes the machine transit to a particular state S1 and this start of conversion was made 1 and then it is made 0. So it is a 1 clock duration during S1 and since this is a function of the start signal what we try to do was that we try to convert that into a milli type of output and you know by making the SOC as a function of start then we say that in this particular state S0 SOC is 1 if start is 1 and when the start is 1 upon the next clock it is translated to the next state S2 because S1 is not required just to kind of make it equal and to compare that is why I called this S2 because calling this S1 will kind of make it similar to that and we have looked at the timing and we have found that for the Moore kind of output the SOC comes during the state S1 but for milli it comes during S0 and also we find that one state is less. So we said in general you have many outputs which are kind of milli outputs then may be the number of states in the state diagram will be less. So the state machine area will be less and also the output comes earlier to the Moore in the case of milli one other thing we have found the problem was that if this particular input is not synchronous then it can change any time and if it changes very close to the clock head you get a glitch at the output and that can create problem and but that happens only when the input is not synchronous and when the input is synchronous we could happily use these suppose in this case we are showing the FSM to synchronous subsystem as I said it could be registers, counters and all working in the same clock then some output is coming and we can now generate this particular output of the FSM as a function of these synchronous inputs. So wherever you have synchronous input you can generate the output as milli type output which will have better timing it comes earlier and it has number of states less and so on. And we have also seen how the state machine generates some enable signal in particular we have looked at the register how this latch signal enables the latching the data from the input side. So that is what we have shown we have a register and the FSM working at the same clock and this latch signal is decoded from a state which is controlling the register. So when the latch is high and the clock comes the data gets latched and a possible implementation was this and we have found the problem with it that it has two kind of active edges come here. The first one may not meet the kind of the timing requirement for the data, second one could create timing problem and if this is used I said to clock a counter it might kind of count twice and so on. And the solution is a recirculating MUX where we move the latch signal or enable signal in the data path and that works properly because that is enabling the input of the register and neatly in the next clock edge it is large enough time is there the only issue with this was that it is clocking all the time either it is connecting the input to the register or it is recirculating and this idea can be applied to kind of any number of inputs not really just enable. So we are showing this as an enable of a counter when the enable is one which has three synchronous with the clock and then the counter is incremented and that is very useful kind of situation that we are keeping track of the state machine is keeping track of some event and event has happened and then we enable the event counter so that the counter can be incremented because say we are working on some communication issue and we are counting the number of bits so when we have kind of done all the processing then we can increment the bit counter and so on. There are lot of applications can be used and we have seen the corresponding code and we have also looked at we have limited to enable we have another load signal then another MUX come which has priority so it comes close to the input of the flip flops. So then we have seen the equivalent code and we said that the problem with this recirculating MUX is that lot of power dissipation and this actually is much better in the power dissipation because only when it is enable it switches it dissipates power the issue is that it has kind of two edges. So if you move this to the negative edge side then if you hand it then you get a single pulse ok the correct location so we decided to resynchronize this enable signal with the negative edge of the clock then this will move here like that and if you hand it you get a neat pulse and that is what we have done in the next scheme here. So the clock this is a negative edge triggered flip flop and enable signal is given to that so it is resynchronized to negative edge clock 1 that is ANDed with the clock and that is used for clocking the register so that is what is shown here this was original enable signal and it is given to the input of this D flip flop. So since it is negative edge triggered at this edge this is latch so there is a tcq delay it appears here and this edge it is kind of sorry this edge that is the 0 is transferred here so you get it here you AND with the clock this clock 1 that is what we do and the clock 2 is a neat pulse and a single pulse you get so this is a kind of clocking scheme for low power and as I said whether you write a VHDL code for this or VHDL code for this many a times can convert this into kind of this particular circuit at the VHDL code level itself it can be you know convert it is very easy to do that and the tools can do it automatically. So that is where we have kind of stopped in the last lecture and let us move on with some more issues of the state machine and once again before going to that just a reminder the state machine structure is like this you have state flip flops keep track of the state the output is a present state which is combined with the input and generate the next state which is latched on the next clock. So this is kind of one path and the next path is that the present state along with the input is decoded for output and if it is more output it is only present state which is decoded. So the Millet output both input and the present state is decoded and we said if you look at this logic and this logic both receive the present state and input and so we can combine this logic in one block only thing is that this output is shown from there. So that is what is shown here this logic comprises of next state logic and output logic the next state logic will give next state the output logic will give the output both are useful for analysing the writing VHDL code and so on. So please keep both in your mind the some text book show this and some text book in your basic courses show this does not matter but then it is better to keep both views in your mind. So let us take up this issue the state diagram optimisation. So when you kind of come out with a control algorithm like we have seen that you have a problem specification then we said that you draw a waveform of the input and output and looking at the waveform you can write a verbal description of what we are in and do many a times and that is algorithm you know formally put it that verbal description can be turned into a proper algorithm with iteration and all that and you draw it and many a times it can be complex and at least at the first state when you do that when the control algorithm is little elaborate complex and you draw the state diagram it may happen that there are identical states in different parts different parts means assume that you are in a particular state depending on the input you branch to different kind of sections and do something okay. So it may happen that in one state in one section is similar to another state in another section and because it is many a times you draw it on a paper it is very difficult to kind of identify that both are kind of identical okay. So this the tool can do it tool can detect the kind of identical or we can even call equivalent you know identical is not a good word technically but we can say equivalent states okay. Now the question arises what are the equivalent states okay definitely from our your kind of experience with the state diagram we can say two states Si and Sta are equivalent at least we can say if they produces the same output okay if it is more than it just produces same output or we say if it is a milli kind of output then we say two states for the same input condition produces the same output they are we cannot say they are equivalent at least they are half the job is done with regard to output. Now we have to look at the transitions also okay now if you look at the transition there are two cases there could be two states which are transiting from the same previous state and there could be two states from which the transition occurs to the same next state okay. So for an equivalent state which one to consider is the question but it is very easy we know that the next state is a function of the present state okay. So if two states are has to be equivalent they should produce the same next state because next state is a function of the present state okay. So if two present state produces the same next state then in that next state Boolean equation this present state appears. So if they are identical I mean they the next state is identical then we can say these states are equivalent. So let us put whatever I have told formally so let us go to the slide. So we say states S i and S j are equivalent if for the same input condition both state transit to the same next states okay. Now when I say same next state S i and S j can transit to S k under the same input condition that means like we discussed earlier there may be an input signal called start and S i and S j will remain in their states when the start is low, when the start is high S i transit to S k, S j transit to S k say assume that these are different parts of the state diagram okay not that do not assume that both are kind of concurrently working when the state machine in S i and the start comes it goes to S k when the state machine is in S j and the start comes it goes to S k okay. Now that is just the simple case may be S i transit not only S j on some other input condition in my transit to sorry S i transit to S k on some condition S l in some other condition. So S j also should transit upon the same condition to S k and S l. So all the transition all the input condition should match okay that is then we have to state the output for the same input condition both states produces the same output okay. For more output you can ignore the input condition does not matter with the more output we do not decode the input. So only the present state matters so that is then we can say S i and S j are equivalent that means for both states transit to same next state for the same condition okay all the transition all the condition should match. These two should produces the same output for exactly same for the same input condition if it is mille with more just same output then S i and S j are equivalent then we can replace S j with S i you know that is a game you know that is simply wherever S j is there rub it off and you know bring those you know arrows which ever was going from S j anyway it goes from S i and output also is taken care there is no problem it works properly okay. So that is how so if S i and S j are equivalent one is redundant then you can remove it and the rule is applicable to more than two states when we formally state we say about two states but then it is easy to kind of formally state it but if three states can be identical under the same kind of condition. Now how to detect this now that the question is that fine we say like in a state diagram like it you know that if there are 32 states spread across an A3 sheet okay you have drawn in a big sheet and how do you look you know you put the finger on one state and keep the other finger on all the other state and looking for and you have to do all the combinations it is a very laborious job. So on a state diagram it is very difficult to do that even if you kind of that does not help a computer algorithm because ultimately if you want to do that in a tool we have to formally state the algorithm. So which is the best place to look so we know that the first one talks about the next state so the ideal place to look for that is in the next state table okay. So what are we looking we are looking the for two states at least let us take two states the two states for the same input condition produces the same output condition. So you go to the next state table pick up the rows okay and wherever you find there are same next state and same input condition and you pick up the present state they are kind of the ideal candidates as far as the next state is concerned. So that is what I state here the first condition can be detected by examining the rows identical rows except the present state because the next state is same and the input conditions are same. So pick up all that then you get the candidate for the present state because you have to now detect whether the check whether the output is same and that can be easily detected in the output logic table output table. So the second condition can be detected by examining the rows identical rows except the present state. So you leave the present state look at the outputs if outputs are same and the input conditions are same then you can kind of for more output you can just look for the identical output then you know then you can pick up those states okay. Now there are we have to kind of make an intersection of two states because this at the end of it you get you know some states if you look at it you get some state and both should be ANDed or intersected then you get the correct thing. So this can be systematically done in an algorithm so let us state that. So in the next state table look for the same next state you know you look where are the next states are similar then out of this next state select the state which have the input condition same. So if you state an algorithm look for the next state which are all similar pick up all that look at the input condition wherever out of this input conditions are same then you pick up the present state then go then go to the output table check if the outputs are same for this next state. So wherever the outputs are same pick up those states and then we have for Millay you have to look for the inputs also you know you have to match the input for Moore you match the output then these states where the outputs are same they are equivalent you know. So systematically you can do that so the tools can do that you know first look for the identical next state then go for look at in these states the inputs condition the next state table if they are identical pick up those go to the output kind of output table check for these states where the outputs and input conditions are same those states will be the equivalent ones and you can remove keep one and remove all the rest then the state diagram is optimized you have to check whether your tool does it maybe when we come to the tool we cannot I am waiting for some more portions to be covered so that we can introduce a tool so that once for all we can find quite a few things also that you know that the tools are changing all the time. So I am in that part of the lecture maybe less useful because after few years if at all this course is used by someone then the tool part is kind of there is no guarantee that you know it makes sense because by then the whole interface and everything would have changed so people will have still is useful to see the design methodology the steps and output and same I am hoping that will be useful but I am delaying it so that we pick up maximum information input so that you understand everything when I demonstrate the tools boards and things like that ok. So let us move on to another issue this we talked about the state diagram optimisation we have in a state diagram how to identify two or more states are identical so that we can optimise a state diagram we can kind of remove the redundant state and keep the minimal state diagram so that the area occupied by the finite state machine is less that is our aim. So let us move on to another issue which is called output raising or output glitches or whatever so forget about the name so let us look at the issue ok. So take a state machine with 3 flip flops ok. So let us call it there must be Q2, Q1 and Q0 so I am just showing a part of a state diagram so there assume there is a big state diagram which kind of at least it has more than 4 states we do not know whether it occupies 8 states but more than 4 states which force us to use 3 flip flop to implement it and there are we call it Q2, Q1 and Q0 ok. Assume there is a transition from 001 to 010 ok. So in this when the clock and there is no input condition maybe a clock comes this transit to this so Q1 is going Q0 is going from 1 to 0 and Q1 is going from 0 to 1 ok. Now assume that see we have 3 flip flops and all may not be kind of has the same propagation delay assume that the Q1 is faster than Q0 that mean TC Q0 is less than TC Q1 ok. The propagation delay of the first flip flop is less sorry the first flip flop TC Q1 is less than TC Q0 or TC Q0 is greater than TC Q1. So what happens is that you see that it was 001 if this is faster this 0 will become 1 before this 1 becomes 0. Then ultimately 1 will move to 0 because Q0 will change state after a while. So what happens is that in between while changing the state from 001 to 010 for brief period a transitory state will come which is 011 ok. So that is what is shown in the picture I have shown in the picture I am saying that the propagation delay of Q0 is slower I mean it is larger than TC Q1 or the Q1 is faster. So Q1 becomes 1 and for some time Q0 remain 1 then transit to 0 so 001 becomes 011 and ultimately it becomes 010 very, very brief period it becomes you know and it happens you know that it is because you know do not worry about it we talked about in combinational circuit when there are multiple output there is difference in the path delay it happens. So similarly when there are multiple flip flops because of the variation in the propagation delay of the TC flip flop this happens is very natural ok there is nothing wrong with this. Now you can take the other condition if Q0 is faster than Q1 so take the other condition Q0 is faster than Q1 means this 1 will become 0 before this 0 becomes 1. So you will get a situation where for a brief period you have all 000 then it transit to 001. So you have the other condition the Q0 is faster so 1 becomes 0 then the Q1 change states 010. So either of this condition if the delay does not match exactly 1 is greater than the other there are 2 conditions there could be a transit to a state 000 or 011 and the fact is that we do not know whether these are kind of valid state maybe this is part of the state diagram some other state. So you might ask the question to ask is that is there any concern to worry about ok it does not matter for a brief period let this happen it is only for a very few maybe say 2% of the time or 1% of the time it just you know transit it does not like it settles anyway ok. It looks little innocuous but assume that these states produce some output ok because this could be valid state in the state diagram or part of our control algorithm assume that there are 2 outputs called enable and write and that is 1 in this state which is valid. So what happens is that when the clock comes and the present state changes from 001 to 0010 these outputs will briefly go active ok. So you see such a situation here the state machine in this state the clock comes so for a and ultimately this the state here is 0 before was 001 and here it is 010 but brief in between it may go through 00 or 011 so if it goes through 00 you get a write pass briefly going high a glitch and an enable pass which is briefly going high if it happens this way ok. Now once again is that a cause for a concern you know is that create some problem now it depends how this particular output is used if this is used like to enable a counter we know that it does not matter because we know that when you enable something using clock gating or recirculating marks nothing is going to happen because we see unless enable structures all over here then only this clock will kind of become active enable the recirculating marks. So it may not in a synchronous case it may not kind of create problem but we do not know how this is used maybe this is used asynchronously to increment a counter or this write is going to an asynchronous memory as a write pulse then what happens that for a brief duration the write pulse go high and if the access time is enough maybe the address line is floating or some value is there data line is floating but then something get latched into some address and which can corrupt some location ok. So depending on like how fast is the memory how fast how you know shortest access time and so on. So this could create problem so that you should keep in mind because this is called output racing because these two outputs 2q1 and q0 is racing each other and one is faster than the other that can produce briefly the transitory state it can produce output this may or may not cause problem and when there are critical applications we have to worry about it like you are making a kind of medical equipment which is used for some kind of radiation and you are designing a controller for it you have to be very careful you know but if you are doing something very not that kind of where such a critical application is not there it may not matter now some user intervention user is pressing a key if it is not detected maybe the user can press it again may not matter. So it depends on the application the criticality of the application you have to break your head about it ok always when you are designing something maybe you are in a huge team ok you are doing a part of the design maybe you are doing front end design you are doing the back end design and you do not know like some people sometime you do the back end design of kind of verification and if you ask what is this used for they may not be even aware which chip they are working on or they vaguely know and they may not even know which is the application it is very kind of very bad situation you if you are working on a design on a big team you should know what are you working and what application it is used. So that you can kind of judiciously you know choose the design practices you know which is how the reliability cost flexibility all that can be balanced properly depending on the application very very important like you are sending something to the space you know and a space vehicle is being controlled it is very critical nothing can be corrected on the way sometime from the ground so you have to make it very critical so it depends where you are or on an aircraft you have to be very careful so let us go ahead. So this is what I have stated earlier now the question is that what is the solution you know there is fine there is an output raise what is the solution ok. Now when you have a problem ok when you have such a problem and when you in general ok maybe you are used to always learning from the textbook there is some problem the textbook tell you some answers but mind you these textbooks get the answer from the research somebody has done you know at the beginning when somebody has proposed a state machine Moor or Milley all these issues would not have been thought about you know that implementation kind of detail. But when you have a problem you should know to solve it in the first place you should know what cost the problem ok then you can attack find a solution say I have heard of a story there was a highway and there was a sharp turn in the highway ok you know the highway is very you know high speed highway is there where the vehicles are going at very high speed above say 100 km per hour and there is a sharp 90 degree turn for whatever reason there is a turn and at night there used to be lot of accidents and the residents are kind of worked out you know they have to call the ambulance service the police and so on. So the residents decided to do something about it and they have met together and somebody suggested that let us station an ambulance you know at the turning so that when the accidents happen people can be picked up and everybody liked the idea you know it is a great thing because whenever the problem happens they used to call an ambulance so if the ambulance is ready nearby this can be attended to ok. So everyone agreed and they were going for kind of one collection to buy the ambulance and some wise men said see the problem has occurred because there is a sharp turn in the highway to solve you have to straighten the turn you know reduce the sharp turn make it smooth then there will be less problem you know and everyone agreed when about doing that. So similarly when you have a problem always think what caused the problem there could be a at least some solution to it and let us see here in the output rays what caused the problem what caused the problem is that we can say that there is a like it looks like that there is a discrepancy among the delay you know in the flip flop there is a kind of variation in the propagation delay ok now if you once again this is not in our control I mean you fabricated and everybody fabricated try to fabricated on the same die very close together but yet when you do the processing the like electrochemical processing there could be a kind of variation but if you think again deeply you see the problem has come because there are two flip flops changing the state that is why the variation in delay is affecting. Because the state assignment was 001 to 011 so 1 is not changing only the Q1 was changing the state. So it shows that if the state transition can be logically adjacent ok or you say sometime the gray coding if the adjacent states like when a state transit from one state to another those states are logically adjacent they change only by 1 bit then this problem would not arise. So at least like from working out from the fundamental cause we can say the solution is that do state assignment such that more than one flip flop does not change output ok well and well and it is good you know it works at least in simple cases you have a state a transit to next state then transit to next state and so on it comes back then you can do say 000001 011 you know the gray code and you can do that ok. But what about all kinds of transition you have a state then a transit to three state from there it goes in a loop from here it comes back to something may not be able to do the you know logically adjacent coding in all cases you take a simple case you have one state here it transit to next state it transit to another state and come back. So three states are adjacent to each other you cannot do a gray coding you know because if you remember the Karnoff map where we do the logical adjacency for Karnoff map we know that the three states cannot be logically adjacent to each other four states can be ok maybe you will say you insert one dummy state in between which does nothing it can be done but then in a complex state diagram and you find there are lot of you know kind of adjacency problem you introduce dummy state then it becomes equivalent I mean complex and lot of areas wasted on that and that is not very bright solution. So if this is possible if gray code is possible do that ok it may not be possible and then what we do is that maybe we can say another issue in the original diagram is that it is because it is producing output maybe there are some transitory state which does not produce it does not change the output then do that the state assignment such a way but very if a state does not produce any different output what is the use of such a state. Though it looks very sound very nicely some solutions sound very nicely but it may not make much sense you know many a times when people talk what they talk sound very good but it may not be practically has no relevance so you have to be very careful when you make statement. So this statement sound good but practically it does not happen if there is a transitory state which produces the output same as before or same as after then you may ask what is it doing ok it may not do any useful purposes. Suppose now assume that you cannot do anything what is the solution now you are stuck with this problem you have a glitch ok then and that creates some problem and you want to solve it what is the solution. So now then let us look at the ideal again what we look at is that how does a good output looks like if enable is a valid output it would have to start from here it would have gone all the way up to here this is a transitory output so it appears as a glitch ok if it is a valid output it extends all the way at least for 1 clock period. So why not we put at the output logic 1 flip-flop and give a clock to it so that this if valid output is registered and get a registered output this glitch won't be registered because it appears briefly for a short duration so that is the kind of the most kind of permanent solution you output the register the output you know and outputs are registered on the next clock edge well after the state change. But output will appear after 1 clock period ok so that is what I have shown here what we do is that you have the output logic you put a suppose there are 3 output put 3 flip-flops for 3 output give the same clock and the reset and this is a registered output earlier we used to take the output here now you look at it suppose we have an enable output which is glitching ok and which is coming here there is a load output which is a valid output then you see the difference like since when the clock comes in this clock edge nothing happens enable is not high the next clock edge when the clock comes here that this glitch would have disappeared so the enable registered remain 0 throughout all the time. But if it is a valid output which starts at this point goes all the way to the next clock period at least this is the worst case 1 clock period it can remain high does not matter. So in the worst in the critical case it remains there for 1 clock period but when this clock edge comes it is high so the registered version of that output comes at the output with the 1 clock cycle delay. So that means that all the glitches go off but all the outputs kind of lag by 1 clock cycle you know lag with respect to the state change ok. But it is a less of a problem you know that in the state diagram these come to the starting state when it starts iterating or start initialising everything is delayed by 1 clock period as far as this particular output is concerned not a problem not a very serious problem. But you should keep that in mind you know there can be side effect if you do not remember that you know that little care has to be taken with respect to the timing you have to analyse the timing what happens because you see that this output is going to the data path and data path is giving some input and this latency can reflect some time in the controlled algorithm. So you have to take care you have to think do not take things just because you state you know solution is there you put the output register and you know assume that everything works you please analyse the timing that you can think of situation where this makes a difference to the control algorithm something need to be tweaked for proper work you have to keep that in mind you know. If you are clever you can find a solution maybe you can solve a very critical problem if you understand the issue but now look at it you know that that is a permanent solution for output raising or output glitch but one thing I want to kind of bring out from this diagram the earlier we said that this output logic and the next state logic gets a input the same input you know the present state is here and input here the real inputs from the data path is input to this stage input to this stage and we combine this state here. So now if you look at this diagram see this stage and this two stage look identical so if you can take this output logic put it here and call logic now that this flip flops and this flip flops are same you know you get the clock and asynchronous reset same. So we can combine this here only thing is that combines output registering as well as the state flip flops so that is what is shown here now the output registering the diagram looks much more simplified you have a set of flip flops which combines a state variable that means if there are 5 states there are 3 flip flops there are 3 for the state variables Q2, Q1, Q0 there are 3 outputs then there are 3 flip flops for output and this is the logic which one part is the next state logic which decode the present state and the input and decide the next state which goes to the state flip flops and there is output logic which look at the present state and input produce output which goes to 3 flip flops to register the output and that comes here out of the flip flops come the present state and the registered output. But one thing you should remember that one good thing happens here we said that a set of registers with respect to the with a preceding logic can be coded in a single process. So though it looks very kind of complex with 4 blocks when it comes to VHDL coding we can write a single process to implement this state machine okay whether the tool detects it we have to check it but at least from what we have learned it is a very nice thing you can write a single process and we will see that maybe in the next I realize that maybe it is wise to discuss the VHDL coding of the state machine soon before we go ahead maybe in the next lecture we look at it how to what are the possible ways of doing the VHDL coding and this is very easy like you write a process to code this register along with the next state logic and output logic. So it is a very simplified coding and you want to generate a state machine with the registered output the VHDL coding is very very easy just put the state diagram and start writing the code you will get it. So that is what we have discussed now the output registering where in when there are multiple flip flops change state others in the same transition then due to mismatch of variation in the propagation delay of the flip flops there could be transitory state which can produce output you know glitches and depending on how these outputs are used this can create problem in our circuit and to solve we said the problem because of the discrepancy or multiple flip flops changing states so gray coding is solution and the ideal solution is to register the output in the next clock edge so that these glitches disappear the valid ones come with the latency of one clock period. And we have seen that when we kind of do a little rework on that structure you get a nice structure which can be the VHDL coding of that becomes very easy ok. So let us move forward to another issue that is the selection of flip flops ok. Now in all our discussion to make things easy we assume that we are going to use the D flip flops all the time we said fine I mean the assumption was that we use the D flip flops but you could use let us come to this you could use other flip flops like JK or Toggle flip flops and so on and let us take this transition the present state to the next state ok. So like there are these are the possible transition 0 to 0, 0 to 1, 1 to 0 and 1 to 1 ok. Now in the state machine if you are using D flip flop ok the sequential circuit use D flip flop to implement the state machine then we know that it is very easy the input to the D should be same as next state you know it is very easy like we do not care what was the present state if the next state is 0 the D has to be 0 next state is 1 D has to be 1 ok. But instead of D flip flop if you are using a JK flip flop ok then that means like in the state machine like what I am talking is that this particular flip flop instead of D if you use JK then you have a J and K then you should know that for each like earlier we had D1 say D2, D1, D0 coming out of the next state logic. But you have now so J2, K2, J1, K1, J0, K0 so in the next state logic we will add twice output for the JK flip flop ok. So if that happens if we are using JK flip flop here then the condition for that to decide when you work out the next state table it will be like that if the present state is 0, next state is 0 then we should disable the set. So J has to be 0 and K is do not care it does not matter ok K can be 1 then it is reset you know the next state is reset it does not matter 0 to 1 J has to be 1 it is a set operation kind of J is 1 and K can be 0 I mean K can be do not care if K is 0 it is a set operation K is 1 then it is a toggle operation does not matter whether it is 0 to 1 can be a set or a toggle similarly 1 to 0 K has to be 1 it is a reset operation. J is do not care if J is 0 it is reset J is 1 it is a toggle because 1 to 0 it toggles 1 to 1 then that it should not be kind of reset so K has to be 0 J is do not care if it is 0 0 no setting if it is J is 1 then it is a setting operation does not matter. So that is what is the transition table for the JK and if it is a toggle flip flop then you know that 0 to 0 it is not toggle so toggle is 0 0 to 1 it has to toggle 1 1 to 0 then toggle is 1 1 to 1 it is 0. So toggle flip flop by which I mean there is an input called toggle and if it is 0 the output 1 toggle if it is 1 the output will toggle that is meaning of it. But looks like in the case of JK the next state logic will have to produce twice the output with respect to D flip flop. So you will find that internal to the next state logic there will be some logic for J2 some for K2 some for J1 some for K1 and things like that and at least for a novice in mind looks like the next state logic in the case of JK could be kind of little complex than the D or T. But mind you you have don't cares in K and J in the case of JK so that could kind of minimize the next state logic area we are not able to say that. So though the JKK is different from D you have the twice the number of output with respect to next state logic because of the don't care the area of the next state logic can be less than in the case of D and T you know that you should keep in mind. And when it comes to the FPGA normally you get D or T flip flops okay, JK flip flops are not there I am not very I do not remember now at least in CPLD you have an option of B and T not because that in the state machine this is useful. But for counters you know that the counter has toggling action like at least the binary counter you know that it counts very sequentially 00001001011 then the next bit is toggled you know. So the toggle flip flops owing to the counter kind of sequence the binary sequence this is useful in the counting application. So the CPLDs and FPGA as flip flop which can be used for the counting and wherever there is toggling application. So maybe we have less time left for the next kind of issue to be taken. So essentially we have looked at the three issues today one was basically we have looked at the state diagram optimisation and wherein we said that basically the issue is to find identical state and that is identical if both produces the same output for the same input condition and they transit to same next state for the identical condition. All the number of transition and number of next state should match then they are identical we have discussed how to kind of identify this from the next state table and output table and some are formal steps we have stated but it can be converted into a algorithm suitable for kind of software can be implemented some tools implement that you can check whether your tool implement it and then we looked at the output racing and we have said the gray coding is a solution output registering is a solution then we have looked at the selection of flip flops and you can use D flip flop, T flip flops or JK flip flops. In the case of JK flip flop the next state logic has to produce twice the number of output but then because of the don't cares the area can be less but practically the FPGAs and CPLDs does not have JK flip flops mostly it has D and T flip flops once again T flip flops are given for kind of binary counting could be useful in the case of the state machine again there are ways the tools can choose the ideal type of flip flop or you can kind of tell the tool to choose a particular flip flop if you are sure of the kind of some kind of advantage you get out of that. So maybe in the next lecture we will go look at the VHD encoding of the state machine since the state machine is an important part we will look at it not that we have learnt all what is required but formally putting it together some kind of something specific to state machine coding can be discussed there. So please revise what we have looked at it go through the timing work out some make some practical cases think of when this is applied to the practical cases what are the kind of side effects it produces try to solve it or if you have done similar work you think you connect with these lectures those who are working in the industry you can kind of relate to what you have experienced what you have done in a project or in a work you are doing now. So please revise it and I stop here I wish you all the best and thank you.