 Welcome to this lecture on programmable logic devices in the course digital system design with PLDs and FPGAs. The last lecture we have seen a fitting exercise in PLD 22V10 that we have tried under some constraints to see whether an 8 bit odd parity generator can be fitted in the PLD. Then we have looked at the programmable technologies like EEPROM, EEPROM flash and how a wired and wired ore is constructed out of these transistors which is area efficient. Then we have an introduction to the complex PLDs which is kind of built out of the symbol PLDs ok which takes Q from the symbol PLDs. So today our focus will be the complex PLD before that we just run through the last lectures the material once. So we have basically seen the 22V10 structure, the macrocell and the summary of it that you have variable product terms, asynchronous preset product terms, synchronous preset product term. You can choose combination or registered output, you can choose an inversion at the output of combination section or registered section to apply de Morgan's theorem and optimize the number of product terms. An example is shown here basic timing details, combinational timing propagation delay and with respect to the flip flop and with or without feedback you know that is that means sometime with feedback you know like you have extra time delay added to the array because of the input delay and all that ok. And we have this was the question we asked 8 bit old parity generator. So it is nothing but 8 2 input exclusive or gates if you consider like that with you know one output is like 2 input bits go to at first XOR gate, the first XOR gate output and third input goes to the next XOR gate and so on. But the main thing is that we assume that this is expanded into product terms I mean that is complete expression is converted in like AX or BX or up to the 8th input is completely expanded into the product term which consists of 2 raise to 7, 1 to 8 product term. And the IO requirements because there are 12 dedicated inputs so 8 the requirement is less than that and one output but there are 10 IO so that is also IO satisfies the resource IO resources satisfies properly but we have to see the product term. And when we turn we assume that it is expanded then there are total 120 product terms possible but we need to cascade, we need to combine everything together in a 2 pass logic. So we need at least 9 product term to cascade because there are 10 total sections are there we take out 1 for cascading. So we have left with 9 sections so we need at least 9 product term to cascade. So we choose a section with maybe the 9 product term so the closest one is 10 one with the 10 so we have to remove the 10 from this 120 so we are left with 110 product terms. So when you expand this XOR implementation it is not possible to fit that into 22V10 PLD but if you like if you think of it as a cascaded 2 input XOR gates they assume that the first 2 inputs come here and 1 XOR gate that means 2 product terms are formed and that XOR gate output is cascaded to the next 2 input XOR gate and so on. You know like a chain in the 8 section then it is possible to implement or you take a tree approach 2 input XOR gate 2 input such 4 2 input XOR gate which will consume all the 8 inputs 4 outputs that can be combined in the next 2 XOR gates. And so you will get 2 output and that can be cascaded in the next section 1 XOR gate say 4 2 1 that is also possible so you can think of various other scheme maybe 3 input XOR gate 3 input XOR gate because 3 input XOR gate when expanded will occupy only 8 product terms so 3 3 2 which can be you know given to a 3 input XOR gate and you get the output. So various possibilities are there so if you the moment you assume internal nodes it is possible to implement but if you expand it to complete product terms it is not possible to implement. So that is what I have written maybe this was not there in the last same I have added that you can think of cascaded 7 XOR gate with 6 internal nodes it is possible to fit a lock structure that is 4 2 1 2 input XOR gates ignore this dynamic this is a mistake lock structure of 3 input XOR gates possible or lock structure of 2 4 input XOR gate that means you have 2 4 input XOR gate. But this will expand it to the 8 product terms you know 2 raise to n-1 and then that output is cascaded into 2 1 2 input XOR gates all these are possibilities various other possible maybe there are other cascading scheme you can apply but these are kind of low delay sensible structures which can be easily implemented. But a default approach of expanding into product terms will not fit into the PLD 22 V10 and the application of a SPLD we have seen it is glue logic random logic you can implement encounters finite sheet machine but this wide decoding is not required for many application one disadvantage is that it has hardly any number of flip-flops just 10 flip-flops with which you can do very minimal thing. But still it is useful when there is more of logic than the flip-flops and the application require less number of flip-flops and more logic than that can be used. And we have looked at the programming technology EEPROM transistor how the transistor is used as a switch in the normal case it acts as a n transistor when charges are trapped here it is kind of it is the gate has no control so it is switched off and we build the ion gate with this kind of transistor and once it is programmed it is permanent it is not volatile non-volatile but if you expose to UV this gets out and it becomes normal transistor. So to kind of remove the connection we trap the carrier charge here by applying a programming pulse here grounding it applying the normal drain voltage it gets you know trapped and it is removed by exposing to UV. So we have seen how an ion gate say a 32 input ion gate is formed with this transistor. So it is simple you have one line which is pulled up these transistors are connected to the ground from the line the gates are the one the inputs you know these inputs like one input is one kind of it is connected to the gate of one transistor second input is connected to second gate and so on like third fourth and so on. So when input is one this is pulled low so that means it is a wired NOR to make it wired NAND we have to invert the input PC because in a PLD both the input and it is complement is available. So wherever the I1 is implemented use I1 bar okay where I2 is implemented use I2 bar because both complement and the signal is available. So just do a swap then it works like a wired AND and then we have a wired OR structure which is again a wired NOR followed with an inverter. So it does not occupy too much you know it does not consume too many transistors as one thing because of this wired structure that is what you know the advantage of using the wired functions and the EEPROM transistor it is similar to the EEPROM and flash is similar to the EEPROM this silicon oxide layer is thin. So it can be programmed by applying the positive voltage programming voltage on the gate electrons get trapped it can be also erased by reversing the condition. So electrons get out so it can be electrically programmed electrically erased only problem is that when it is not programmed this conducts normally because of its construction. So you need to put this transistors in series with a normal N transistor and suppose you do not want I2 to kind of make a connection to this wired AND gate then you just cut it off then it has no effect now it is like whether it is 1 or 0 it makes no effect because it is cut off. So that is how it is programmed and the wired AND and wired OR is formed and the programming uses a standard file called ASCII file called ZEC and the usual normal IO pins are used to program it there are address pin, data pin, control pin, program pin and all that. So the programmer will apply a programming pulse to program pin then these functions of this program pins are exposed to the user IO pins and that is programmed and then in the normal mode these IO pins can be used that is how the SPLE is programmed and that needs a separate programmer you cannot program it within the circuit okay. So it cannot be programmed in circuit it has to be programmed in a programmer erased in a programmer but put to the board. So essentially it means that you cannot use some packages which can be directly mounted onto the PCB if it need to be reprogrammed okay if it is kind of one time programmable the design is frozen the designers are sure about it then it can be kind of mounted on the PCB directly no problem and we looked at the complex PLE and we said that there is no point in like you take a 22V10 kind of PLD and this already is quite huge you know you take there are section with 16 product terms and which many a times one does not require that and each AND gate is kind of 44 input AND gate. So it is a very wide AND gate with lot of product terms and now there is no point in blowing this up as I said you know there is no it does not make sense to have a 100V50 that means there are kind of say like 200 vertical lines and 50 outputs with huge number of product terms but what makes sense is maybe replication of these kind of 22V10 structures which is interconnected okay so that is what is a complex PLD is that simple PLD sections are interconnected. So the requirement is that output of any block like you have a SPLE block output of any block should be able to go to one or more input of other blocks suppose we have 4 blocks SPLE block one SPLE output any of the output should be able to go to any of the inputs of the other 3 blocks then only we can cascade and implement some useful function. Similarly you have input signals okay that those input signals should be able to go to one or more inputs of any block okay and now so the complex PLDs or CPLDs are hierarchical PLDs. So these are the simple PLD section interconnected okay so there is a product MRA that is nothing but RA of AND gates not big numbers like 22V10 where there is 8, 10, 12, 14, 16 these are small numbers say 5 product terms but there are ways to expand it we will see that and the macro cell is nothing but a flip flop with bypass and choice of the clock lines, choice of set and preset, choice of clock enable and so on. Now this the product M itself is not kind of permanently connected to an OR gate so in between comes a switch called product M allocator or distributor which allocates this product M to the OR gate or to an XOR gate or to control various functions of the flip flop okay. So we will see that maybe you can use a global clock pin to clock all the flip flops or you can use a product M as a clock okay or you want to reset the flip flop you can there is a global reset pin that can be connected to the reset of the flip flop or a product M can be connected it depends on the design maybe that in the design there is an FSM which need to reset a counter under some condition. Then a global reset would not help global reset helps during the power on at the power on you can bring all the flip flops to some required state but if an FSM need to control a particular reset then you need to have the product M as reset and that is done by the product M reset which is that this allocator does this allocator allocates a product M for not only for AND gate and sorry OR gates and XOR gates even to the control inputs of the flip flop okay. So let us come back to the slide then you have IO cell basically which is these are pins with tri-state gate which can be used as output and input and at the end is this programmable switch which connects the various PLD section okay. So we have various PLD section I have programmable switch to interconnect them not only the programmable section the IO cell also within each PLD section you have product MRA product allocator or distributor and macro cell okay. So let us so essentially it means the 22-eaten like sections are replicated okay. So we have seen the manufacturers Xilinx as XC9500 and Coolerunner, Altair as max 3000 and 7000 max 2 and 5, Atmel as ATF 15, Ladders as ISP and MAC and things like that okay. So here this is the Altaira max 7000 CPLD this is taken from the Altaira data sheet I will be using the data sheet of both Altaira and Xilinx because some diagrams are good in Altaira some diagrams are good in Xilinx the architecture is kind of similar. So you need not worry maybe specific the numbers input output and all may vary between the devices but otherwise the architecture is similar. So you will be able to you know understand by using a mix of Xilinx and Altaira device diagrams okay. This is what I call a simple PLD section the Altaira called a lab logic array block A, B, C, D. So depending on the device there may be 2 blocks 4 blocks 8 blocks 16 blocks 32 blocks like that you know. Now each block you see there are 16 macro cell that means there are 16 sections of AND or and flip flop okay. But it is all fixed it is not variable like 22V10. So you have 16 macro cell when you say macro cell it includes everything the AND gates, the distributor, the flip flop all the programmability everything is together is called macro cell in this data sheet. My description kind of is little different I combined the flip flop and associated thing I have called as macro cell but this is just a matter of kind of name do not worry too much about it. So now you look at this you have a macro cell section the input of it. So here we have 36 input comes from a huge switch okay. So you can think of it as a cross bar okay we will see what is a cross bar. But this switch output is connected to the input of the AND gates okay. So that is programmable. So you have 36 means 36 inputs and it is complement is available as a vertical line as in the picture okay. So and you have an AND gate and the few AND gates go to an OR gate, XOR gate and flip flop and so on. So there are 16 flip flops, 16 section, 16 output and that can be connected to 16 IO pins or it can be fed back you know it is not that it can be just taken an output can be fed back to the array back. So that the idea is that this output you implement some logic function the output of it can go to the input of some other section maybe it can go here it can go here it can go here some of it can go here some can come here and so on okay. So all that is available okay and in addition to that you can see that not only the output goes to the IO pin and it is fed back to the array you have IO pin itself acting as input and that inputs can come straight as input to the this huge switch okay. Now you see this switch if you take just assume there are only two sections okay to make the description simple this is not there this is a device with just two blocks two laps then we have you see 16 plus 16 32 plus 32 64 input to the switch and 72 output 36 plus 36 72 output from the switch. So when you say cross bar it means that like all these 72 inputs can be any of them can be connected to this sorry this 64 can be connected to any of the 72 maybe the first pin can be connected to 10 then 15th 7th can be connected to 6 and 2 and 9 can be connected to 1 and so on. So all possible connections are possible that is called and why it is called cross bar is that you know the inputs come like a horizontal row and the output goes as vertical row and the intersection you can assume a switch then all possible connections are possible that is why it is called cross bar which essentially come from the telephony old telephony nomenclature it is those exchanges used to be cross bar because if there is a 10,000 line exchange in principle 5000 people can conduct 5000 people okay. So that is how like you that means it is a if you imagine 10,000 line exchange then it is a 5000 by 5000 cross bar 5000 into 5000. So for any 5000 can conduct any other 5000 that was the idea. So that is the basic architecture we will see the internal detail but you see here there are additional signal one is a global clock pin there could be multiple of them in this particular CPLE there is only one and that goes to this all the sections you know the same thing goes to all the sections basically you can choose to clock your flip-flop with this clock okay if needed it is not that you are limited with it you can use a product term to clock it but you can use this also. If you are not using this as a clock then it can be used as an input to the it is not wasted like as a dedicated pin if there is no global clocking you are using then it can be used as an input to this switch and can be taken as input to one of the logic block okay. Similarly there is a global clear that is a asynchronous reset which can be connected to the flip-flop once again if it is not being used it can be used as an input to this huge switch okay. And similarly you have output enabled because there are tri-state gates which can choose to output enable either of them depending on your need or you can choose you know to permanently enable it permanently disable it and so on. So, in case if it is not being used again not waste the pin that can be used as input to this crossbar switch okay. So, that you should keep in mind so this you know explain the architecture from the top level architecture how the logic blocks are arranged, how it is interconnected, how the output is able to go, output of macrocell is able to go to the IO pin as well as to the input of various section. The IO pin itself various IO pins can go to the inputs of any of the section you know that is what is shown here. So, let us move on so it is a crossbar switch. So, we have this programmable interconnect array is a crossbar switch satisfying the connectivity requirement discussed before. It means that any output can be connected to any of the inputs, any IO pin can be connected to any of the inputs that is the requirement. N by N crossbar can be implemented using N, N to 1 multiplexer we will see that. Interconnection between blocks use just one switch okay. So, it means that when you take an output from a macrocell and connect to the input of a macrocell it need only just one switch okay. We will see that as when we go to the FPGA when you interconnect some output input most of the time it encounters lot of it goes through lot of switches. But in a PLD like straight from one output to one input there is just one switch programmable switch. So, this interconnection is very fast and the timing analysis is also fast like when you want to do timing simulation the timing model of the device itself is simple. So, it is very fast the timing analysis is simple. But the problem is that this crossbar won't scale well because if you so this can become very huge because in one section itself it is 74 cross 32 switch and you can imagine if there are 16 section this switch will be very huge and so it cannot be kind of expanded to lot of macrocell you cannot say millions of macrocell then this switch will heat up all the space occupy lot of area and then because of the area the things can slow down okay. So, I am showing an example of a 2 by 2 crossbar. So, you have two inputs I0 and I1 put O0 and O1. So, the requirement is that any of the input should be connected to any of the outputs. So, you put a 2 to 1 max for each output with a select line and inputs are connected to two inputs. Now by selecting S0 any of the input can be kind of taken to the output for both and if you want I0 to be connected to both it is possible there is no problem there is no clash it is not that you can connect only one input to one output it can go to multiple output. So, if you have a you can imagine if there is a 16 by 16 crossbar then you will have to the each output there are 16 to 1 max connected and such 16 of them. So, that is how an n by n crossbar require n, n to 1 multiplexes. So, you can imagine if you have huge switches these very wide multiplexes are required and that can occupy lot of area and the delay can be quite high in that case okay. And these are the max 7000 devices you have EPM 7032 it means there are 32 macrocell. So, basically each macrocell has 16 each logic array has 16 macrocell. So, for 32 macrocell you need 2 of such section for 64 you need 16 into 4 of them. So, that is what is shown here 7064 need 4 logic array blocks and it has 68 pin. So, you can imagine this as IO pin plus the clock output enable and VCC ground and things like that. So, that is how it comes. So, the highest one is there are 16 logic block which is which has 256 macrocell. It is quite a you know big device with lot of the macrocell 256 macrocell is quite high and you can implement many medium complexity design in such a CPLD. So, let us move on. So, this is the crossbar of the silings XC9500 this is not the crossbar of max 7000 it is a silings XC9500 crossbar. I just wanted to show the picture and that was clear in silings data sheet. So, you have an IO pin there is an array like which is here and a distributed flip flop and the bypass and such 16 outputs are coming to the 16 pin and you can see that that is also fed back to the crossbar switch to be kind of you know you can take that into the various logic blocks. And similarly the input is also coming as input to the crossbar switch which can be taken inside the logic block. So, that is how the crossbar is formed this the outputs of the macrocell as well as the input IO pin input is going as vertical line and the AND gates can take you know choose any of them by programming the crossbar okay. So, depending on how you design how you code these switch status will be decided okay. So, basically your VHDL code will be converted into this kind of what switched to program at the end okay. So, that is a basic game. So, this is the real macrocell okay or the logic part of the one section. So, you have one IO pin which is with a tri-seat gate and all that which is not shown here. So, what is the one section circuit is shown here. So, basically you have to look at 5 AND gates okay. And you see one of the AND gate is fed back into the array itself okay. So, this is kind of can be cascaded this AND gate can be cascaded to other AND gates. And there are 16 section like that. So, there are 16 AND gates from each section can be used by any of the section. It is not that this AND gate from this section can be used only by this particular section it can be used by other sections also other macrocells also. And you can see this is the input signal from the crossbar or PIA programmable interconnect array. So, there are 36 signal coming its complement is taken. So, 72 vertical lines which can be programmed to the AND gate to form the product terms for whatever requirement. So, basically 5 AND gate 1 AND gate is an expander product term which is fed back into the array. So, there are 16 sections. So, there are 16 expander product terms. And now this is a normal OR gate which AND gate output goes. But mind you this is not permanently connected. There is a switch here which is called product term allocator or distributed or silings call its product term select matrix. And that allocates the AND gates to the OR gate or XOR gate or various other purpose which we will see that. So, this is a kind of a switch which you know you can choose an AND gate whether it should be connected to OR or XOR or this inverter and so on okay. Now, let us look at the flip flop you see that the OR gate output is going to XOR gate output input and XOR gate output is coming to the flip flop input. And the flip flop Q is going to a bypass MUX. So, here there is a 2 to 1 MUX which get the output of the flip flop as well as the input of the flip flop. So, if you choose this path then you are not registering the output you are taking it directly. So, if you want to implement some combination circuit without register then you can use this path the tool will choose this path. And you can see that this flip flop can be used as a D flip flop or a T flip flop. So, if you have counter applications you can program it as a T flip flop it has a asynchronous reset which you see can be controlled by a product term. So, that is how the switch comes suppose you want to reset it using this product term it is possible there is a connection here which the switch does and then you can reset that. Similarly, there is a asynchronous clear pin which now has two options one is there is a global clear pin for the PLD chip. You can use it to clear along with all the resist all other flip flops or you want to very under some condition you want to clear it. Then you can use this line and the product term allocator can allocate an AND gate to this. So, depending on some condition you can reset it okay. And what we are left with is a clock and the clock enable. The clock enable is nothing but a recirculating MUX with the select line as enable. So, maybe I can show that we have learned that when you want to control a register what you can do is that you can put a 2 to 1 MUX. And if that condition is satisfied this input goes there and otherwise it retains its value. Now, when the max 7000 flip flop as a inbuilt recirculating MUX and the select line of the MUX is called clock enable. So, you want to kind of do such a structure just connect this select line here. Now, the condo signal here you do not need to do anything and automatically it works. So, that is what is this clock enable is about enable A and now you can have permanently enable it or you can control with a product term okay. So, it is quite versatile you know you have 5 product term one of it is an expander product terms. And this can be distributed to an OR gate set clear the clock enable and so on. So, very flexible the device is very flexible. And you can see there is a fuse which is a programmable register that means you can choose depending on the value program here it will become a D flip flop or a T flip flop. So, you can imagine a simple circuit where it can buy 1 out of 0 you can switch between D and T maybe you can think of such a circuit it is very simple. Now, not only that you know you see here there is one issue you just have 4 product terms anyway one is common. So, 4 product terms only or combined with this 5 or some common things, but many a times you want to implement say 10 product terms. Then what you can do is that suppose the previous macro cell as unused product term say for some reason suppose the previous macro cell used only the flip flop then what can be done is that that unused product terms can be steered to the input of this OR gate. So, basically you can cascade the unused AND gate from the previous adjacent section to the OR gate. So, it is a great advantage because if you need more than 4 product terms or 5 product terms then if there are some product terms which is left unused that can be kind of steered to this OR gate through a cascade of steers you know it goes all the way like if the previous section is not used here it can be used in the next section and so on ok. And it can go in some devices only in one direction in some other devices it can go in both directions and so on ok. So, I think you get a good idea and or and this XOR gate now can get the input from one of the AND gates. So, XOR gate can be used for you know the product term optimization as I said you can apply de Morgan's theorem and instead of having Y here you can implement Y bar inverted and take the Y there if the number of product terms are less it can be used for programmable polarity that if it is 1 it is inverted if it is 0 it is not inverted it can be used for arithmetic circuit like half order full order or for parity all that you know all kinds of use you can make use of this XOR gate so that is pretty much the architecture of the macro cell and so the summary of that is that you have 5 product terms per macro cell you can choose between D or T flip flop. Flip flop can be bypassed for combination output XOR gate for polarity PTE optimization comparator arithmetic circuit parity you have product term set product term reset or global reset global clock or product term clock product term clock enable all that is possible in this architecture. Now mind you in this device suppose you had a say an input synchronization has to be done we have seen how a single state synchronization can be done. So there is a signal which has to be taken to a flip flop to synchronize it. So in this max 7000 CPLD if you want to synchronize it it has to suffer an IO delay it has come through the switch and switch delay it has a gate into ion gate then the OR gate then it has or one of the ion gate output can be connected to the flip flop. So it is before getting to the flip flop it suffers a lot of delay. So it will be good for input synchronization directly one of the input can be taken into the flip flop. So such a thing is possible in max 7000 S they have apart from all these connection from the IO pin there is a direct connection to the flip flop which allows low setup time otherwise you will have to set up the input if it is taken through the cross bar you have to set it up much before the clock edge. But with this it is can be set up very fast you know little time before the clock edge it can be set up and that is the advantage of this and that is so from the IO pin there is a direct connection to the max before the D of the flip flop. So you get output of XOR gate or from IO pin directly for the fast input and that is pictorially shown like here you can see that the max 7000 CPLD is like this max 7000 S is little different everything is same you have input you have output feedback IO pin but you can see that from the IO pin there is a direct connection to the flip flop inside ok. So here, here, here like that so it has some timing advantage so if you choose max 7000 S it has some timing advantage it has instead of 1 clock it has 2 clock it has a output enable which is little more elaborate and so on ok. So that is about max 7000 S. Now let us take an example we want to see like say we are showing a code how this code get translated into that CPLD architecture. So look at this which say process clock reset begin I hope you remember the VHDL we have discussed. So if reset is 1 then Q is 0 else if clock event clock is equal to 1 then under that if enable is 1 then Q gets AX or B ok. So naturally upon this is an A flip flop with asynchronous reset and a clock and this enable naturally we know that this AX or B should be connected to the D input of the flip flop because it is synchronous upon the clock if Q has to get that it has to be connected to the D but there is a control if enable is 1 then only this should happen otherwise the Q will be the previous Q ok that is the meaning of end if there is no else and this shows the memory ok. So that is implemented easily through a recirculating max. So the synthesized circuit will look like this you have a flip flop the clock goes to the clock reset goes to the reset and the Q is coming back to a 2 to 1 max and enable select line of the max is connected to the enable. So when enable is 1 this AX or B goes to the D otherwise it retains and if the reset comes it becomes 0 ok. So that is how basically it is implemented now if you look back at the architecture you can see that we need an XOR gate. So XOR gate can be implemented here. So taking 2 inputs here A and B and A can be connected here B can be connected through the OR gate here ok and enable signal as we implemented that can be connected because the recirculating max is built in that can be connected to another AND gate. So then we have the clock and the reset and all that. So that is what I am going to show that. So this is the code upon the reset Q is 0 upon the clock if enable is 1 then Q is AX or B and that is the circuit A flip flop with a recirculating max select line is enabled and to the 2 to 1 max you have AX or B. So naturally this is built into the flip flop so we connect the AX or B output to the D directly ok. So look at this diagram so we have the flip flop we have a reset global reset. So that is connected through this switch to the clear so that it is when it is reset asynchronously it is cleared. We have only 1 clock so we can assume it is global clock so this switches program for the clock and you have A and B pin which I am not showing which is going to the cross bar switch and the cross bar output is coming here to say A is coming to this AND gate B is coming to this AND gate and this particular AND gate goes to the one of the OR gate input and go to XOR gate and B directly goes to this AND gate and go to the XOR gate here. And we have an enable signal which again comes through the IO pin and the cross bar switch and come directly through the switch to the enable because that is there is a recirculating max built in and the Q is taken directly to the pin. So if you write a code like that then this is how the macro cell gets programmed in addition to that you know that there will be A and B pins connected here and which will be taken through this the cross bar into this array okay and similarly enable. So that you have to remember there is more programming within the cross bar switch. So that gives you an idea and this can be easily worked out you know given a code we have seen how given a code you can infer the synthesized circuit and we have learned enough about the architecture of PLD and CPLD and you can work out the connections and you can even estimate how many what all the sources are used within a CPLD. So that is the power of it by understanding the low level details rather than you know just writing the code and hoping that everything works properly. So you are able to suppose I give you a counter and if you work out the equation and you will be able to come and you know infer the circuit out of that VHDL code then infer the connection in CPLD and you can see how many pins of the CPLD is used how many macro cell how many product terms to that detail you can go and some of the tools allow you to see this detail within the device and you can view that and kind of verify that it is right you know that what we have kind of estimated is right ok. So this shows let us move to this kind of this product term select matrix I am going to this is an Altera data sheet but this for that I am going to the Xilinx XC9500 product term allocator which may be little different from the Altera because there may not be an expander product term but nevertheless it shows the idea of the product term allocator. So you can see there are 5 AND gates and there are OR gates. So you can see that this AND gate output one of the like there is a demarc one input is connected to this AND gate sorry OR gate and this one also can be connected. So all the 5 are connected to 5 input OR gate but not that you see that if you are not using this product term for this OR gate it can be used for setting it ok can also use a global set or reset. Similarly take this product term it can be used and this can be used with the OR gate or you know to as an input of XOR gate. Now XOR gate itself can be can in one of this input of XOR gate can come from a product term it can be permanently one by you know kind of controlling I mean inverting the signal or 0 by letting it through similarly this one can go to OR gate to clock it or and this one can you know go to the OR gate it can go as clock enable it can go as product term reset and so on ok and this can go as a output enable. So the design is architecture is little different between the max 7000 and XC9500 but this shows the steering product term steering all these 5 product terms are odd and given to this structure which can be taken to the upper macrocell and lower macrocell and you can see that what happens in that upper macrocell and lower macrocell is that. So this is coming from the upper macrocell that means that there is a section there with 5 product terms and there is an OR gate XOR gate that is kind of diverted here and now you see you can take that and put this is connected to this OR gate. So you can cascade the previous AND gates through an OR gate right down here. So if you have more than one product term and this goes through so it can be like you can you can see that it gets combined there. So you can and so if you look at this section you see this 5 product terms can be combined with the previous one, the top one and the bottom one. So you have 15 product terms that can go up or down which wherein it can be taken to the OR gate of that section. So that is what is this product term steering is what we are calling. So you can if you are left with if you need more than 5 product terms that is possible by product term steering. So basically these are demultiplexes at the output of product term which then can be steered to the XOR input product term clock, clock enable, set reset, steering and all that. Basically it is steer you know that steer from the upper to lower combine various sections and use it and all that. So it is quite useful and if you look at the max 7000 S IO control, there will be a tri-state gate as IO pin. There is output if it is enabled input it is disabled. So there is a max by which you can permanently enable, permanently disable or you can choose the various output enable from this huge switch because we have seen there are output enable multiple output enable pins which is coming to the product term this cross bar. So either it can come through the cross bar to this or some product term can control the IO status of a particular pin. So it is quite flexible under some product term which is in some other block can control a particular pin you know. So that adds to the flexibility. This is the timing model of the CPLD max 7000. So it captures all the delays. Suppose you have a signal which is coming through an input pin. So there is a delay ingot it goes to the cross bar it incurs a delay then it goes to the logic array. So it an AND gate delay is incurred and if there is an expansion by parallel expander additional cascading is added. Then if it goes to a flip flop setup time is added and if it goes to the tri-state gate there is a delay. So similarly if there is an input there is an IO delay and then again it is PIA or for fast input it directly comes to that max delay and come to the flip flop. So the timing model is very simple and the tool basically tool use this model to estimate the time but you yourself can put this picture and estimate the timing manually without even writing a code you know that is possible to do that if you have the idea of the circuit you want to implement. Basically the timing model of the PLD is very simple that is what I want to convey. So when we come back CPLD versus FPGA so though we have seen the FPGA basically the PLD still use an AND or structure to level number of registers are very small which is not the case with FPGA. Timing is simple which is little complex in FPGA. Architecture variation that means across the manufacturers they have the similar architecture the programming technology is flash and the capacity is kind of 10 gate maybe we will look at the FPGA part after going through the FPGA. But the basic thing is that it is non-volatile up to kind of medium complexity or low complexity can be implemented and it is very fast you get reasonably fast implementation and number of registers are small. So you cannot think of the FIFOs and memories and things like that it is very difficult to implement. So the application is that very small design comprising of counters finite sheet machine small logic all that those are the target application maybe you can build a memory controller DRAM controller a protocol translation some optical encoder small control circuit for instrumentation power electronics data acquisition and things like that. So small and medium kind of application you cannot you can use this CPLD. But designs which require lot of registers and memory cannot be implemented in this like signal processing like various filters complex arithmetic circuit packet processing modems codex like the cryptographic circuit all that will be difficult to implement in a CPLD. So that is the limitation of the CPLD. So I think we have come to the end of the CPLD what we have seen today is basically the CPLD architecture how it is a hierarchical PLD is formed out of symbol PLD sections. So there are logic blocks a crossbar which interconnects which allows the output to go to the other inputs IO pins to go to any of the inputs. And then there is a product terms product term allocator which allocates it for various things a flip flop with clock enable the recirculating MUX fix you have the set reset which can come from globally a product term. The clock can be global clock or the product term clock enable us can be global or the product term. And there is in some cases there is a fast input and we have seen the crossbar is nothing but multiplexers at the output. So N by N means N, N to 1 multiplexer product term allocator is nothing but demuxes at the output product term. So that it can be connected to various other inputs like or XOR and flip flop controls and things like that. And there are additional or gates which can be kind of used to steer this unused product term to the next section and chain it you know like that to build quite a bit of product terms. And it varies from device to device how it can combine but you can refer to the data sheet. And we have seen the timing model which is very simple and we have seen the application you can use kind of best product called translation DRAM controllers small power electronics instrumentation data acquisition control circuit can be implemented using CPLD. CPLDs are also ideal for the counters have some small random logic all that okay. But it cannot implement lot of memory complex arithmetic and so communication signal processing computer architecture applications may be out of it networking all that will be out of it but then CPLD has use as advantages. So we should focus on the advantages and use wherever it is required. So I wind up here the CPLD part we will in the next lecture we will move to the FPGAs and please revise it try to understand that that will be very useful and I wish you all the best and thank you.