 Hello and welcome to this presentation of the SPDIF-RX block. SPDIF stands for Sony Phillips Digital Interface. The SPDIF-RX block is able to receive digital audio streams compliant with the IEC 60958 and IEC 61937 standards. The SPDIF-RX embeds an Advanced Peripheral Bus or APB interface allowing the control of the block and the reception of audio and control flows. The SPDIF-RX also provides status registers so the application can check the quality of the reception. The SPDIF-RX needs two peripheral clocks, an APB clock for the register interface accesses. A kernel clock, named SPDIF-CLK, is used for the resampling and processing of the incoming stream. The receiver part is mainly composed of the SPDIF-FE, which performs the sampling, the filtering, and the edge detection of the incoming stream. The SPDIF-DEC, which decodes the received symbols, and the SPDIF-SEQ, which checks the frame format integrity and separates the payload from the control and user information. The SPDIF-RX provides the following features. The possibility to select one audio stream among the four inputs. Note that only one stream can be decoded at a single time. Automatic symbol rate detection. If the SPDIF-CLK frequency is high enough, the SPDIF-RX will be able to decode the incoming stream and provide to the application information about its estimated sampling rate. Stereostream rates up to 192 kHz are supported. The SPDIF-RX decodes audio frames compliant with IEC 60958. This specification describes non-encoded stereo streams. The SPDIF-RX also supports encoded audio streams, such as Dolby Digital, as described in IEC 61937. In addition, the SPDIF-RX provides two DMA channels, one dedicated to the audio samples data encoded or not, and one dedicated to the control, status, and user information. Interrupt capabilities are also available for various signaling. The RCC or Reset and Clock Control block of the STM32F7 provides both the APB clock and the SPDIF-CLK kernel clock to the SPDIF-RX. The SPDIF-CLK is generated by the post-divider P of the PLLi2S, allowing the application to adjust the SPDIF-CLK frequency. The signal SPDIF frame sync provided by the SPDIF-RX is connected to a timer. The application can use it to perform a clock drift estimation in between the two audio streams. Refer to the training slides of the RCC for more details. The next five slides give a short overview of the SPDIF standard. They mainly describe the physical and logical structure of the digital audio stream. In IEC 60958, the digital audio stream is organized in block structure in order to decode the channel status, or CS, and user or U information. Each block contains 192 frames. Each frame contains two subframes. The SPDIF-RX is able to recognize the start of block, the preamples, and the frame boundaries. An SPDIF frame contains two subframes. Each subframe contains 32 bits divided into three fields. A synchronization preamble allowing the detection of the block and subframe boundaries. A payload of 24 bits. And status bits, V, U, CS, and P. The digital audio data are coded using biphase mark encoding as shown in the upper figure. Note that with biphase mark encoding, there is a transition at the boundary of each bit. The preamble length is four bits, and some transitions on the preamble do not respect biphase mark encoding. This will be used by the SPDIF receivers to easily detect the block and subframe boundaries. UI means unit interval. It represents the shortest nominal time interval in the coding scheme. Bits 4 to 27 of each subframe can also be used to transfer encoded audio signals. This is described in specification IEC 61937. The encoded data packet uses bits 12 to 27 of each subframe. The 64-bit burst preamble is a specific pattern also located on bits 12 to 27 of four consecutive subframes. It is used to detect the start of a data burst. Note that the burst preamble, 64 bits, shall not be confused with the subframe preamble, four bits, used to detect the subframe and block boundaries. The first 32 bits of the burst preamble are a fixed pattern, PA and PB. The last 32 bits of the burst preamble contain information on data packet and payload size. Stuffing is used to adjust the repetition rate of the data burst. The SPDIFRX is able to suppress glitches, increasing reception reliability. In order to decode the incoming stream, the SPDIFRX estimates the duration of one UI and defines two thresholds. The low threshold, TH low, fixed to 1.5 UI. The high threshold, TH high, fixed to 2.5 UI. When both thresholds have been computed, the SPDIFRX compares the time interval between consecutive transitions of the incoming stream to those thresholds. If the time interval is lower than TH low, a short transition is detected. Note that two consecutive short transitions correspond to the simple one, but can also be a part of the preamble pattern. If the time interval is between TH low and TH high, a medium transition is detected. Note that a medium transition corresponds to the symbol zero, but can also be a part of the preamble pattern. If the time interval is lower than TH low, a short transition is detected. Note that two consecutive short transitions correspond to the simple one. In order to decode the incoming stream with good reliability, the estimation of the thresholds TH low and TH high must be accurate. The TH low and TH high thresholds are estimated in two steps. The course synchronization measures consecutive time intervals within 70 transitions, and then selects the longest and the shortest time intervals. These two values are used to compute a first estimate of TH low and TH high thresholds. Thanks to a course estimate of TH low and TH high thresholds, the SPDIFRX is able to decode SPDIF frames, and then further improve the estimation of TH low and TH high thresholds by measuring intervals over 24 and 40 consecutive symbols. The figure shows the hardware process performed by the SPDIFRX in order to properly estimate the TH low and TH high thresholds. Note that the course synchronization may become inaccurate in a noisy environment, and the fine synchronization may fail. This can be considered as a normal situation, and the application can program an amount of retries, or NBTR. Note as well that the TH low and TH high thresholds are updated every frame. The figure shows the different states of the SPDIFRX. The state of the SPDIFRX can be changed by the application via the field SPDIFEN or by the SPDIFRX hardware, mainly if errors are detected. When an error is detected, the SPDIFRX directly moves to state stop. It is up to the application to set the SPDIFRX to state idle, and then set it again to state sync or state RCV. The SPDIFRX offers a 32-bit double buffer for data reception. The application can read the received data using DMA or interrupts. Various data formats are available, right-aligned, left-aligned, or compact format. The compact format can be interesting when the SPDIFRX is receiving encoded audio frame. In addition, the SPDIFRX can insert a preamble type, C and U bits, validity bit, and parity error bit with each audio sample. Using the mask bits, the user can select which information will be provided. The SPDIFRX offers a 32-bit buffer for the reception of the CS and U channels. The application can read the received control information in the SPDIF CSR register using DMA or interrupts. The SPDIF CSR register contains 8 bits of CS coming from the selected channel, could be channel A or B, 16 bits of U, the U bit of channel A, and U bits from channel B. And one bit indicating if a start of block has been detected. A complete error signaling is provided to the application in order to define the root cause of any failures. The FERR flag detects errors linked to the frame structure. The SERR flag detects synchronization failures. The TERR flag detects when the counter used to estimate the width between two transitions overflows. This generally means that no signal is detected on the selected SPDIF input. The PERR flag detects if the parity check fails, and the OVR flag detects if an overrun occurs on the data flow. The SPDIFRX can recover from an overrun situation without misalignment. The RxSTEO bit indicates how the SPDIF reacts to an overrun situation. If RxSTEO equals zero, the SPDIFRX can minimize the amount of data lost. To be used for PCM mono mode or the reception of encoded audio signals. If RxSTEO equals one, the SPDIFRX can avoid the misalignment of stereo samples. Must be used for PCM stereo streams. The SPDIFRX offers a single interrupt line shared by several events. Error events, data and control flow reception events, synchronization ready event, and block detection event. In order to have a reliable decoding of the SPDIF stream, the SPDIF CLK frequency must be at least 11 times higher than the symbol rate. The table gives the minimum requested frequency for the SPDIF CLK clock according to the sample rate of the SPDIF stream. The SPDIFRX provides information allowing the application to estimate the sampling rate of the decoded stream without having to decode the CS channel. The accuracy of the sampling rate estimation is partly limited by the frequency of the SPDIF CLK. The application can also check the estimated TH low and TH high thresholds for debugging purposes. The SPDIFRX also provides a signal named SPDIF Frames Sync, which can be connected to a timer in order to estimate the CLK drift. This feature can be useful if the circuit receives audio samples via SPDIFRX, performs audio processing, and provides audio samples to an external audio device. In this case, a sample rate converter may be needed to perform the rate adaptation, which may require the CLK drift estimation. The SPDIFRX can receive signals from an SPDIF digital input, an SPDIF optical input, and an audio return channel from an HDMI connector. A signal adapter may be needed in order to amplify the signal received from the SPDIF interface, 200 mVPP. Using one or two unbuffered inverters can be sufficient in most cases. Note that for SPDIF encoding, the signal polarity can be inverted without affecting the decoding. Only the transitions are used by the receiver. Here is an overview of the status of the SPDIFRX in each of the low power modes. SPDIFRX operations are not possible when the device is in stop and standby modes. This is a list of peripherals related to the SPDIFRX. Please refer to reset and clock control and direct memory access controller trainings for more details on possible configuration.