 Hello, in this section we are going to take our first look at the STM32L0's Ultra Low Power Peripherals. If we look at the block diagram, all the modules highlighted in green are in some way connected to the low power domain. Some can still run whilst the device is in the various low power modes, others have new low power features and the remaining modules have the ability to weight the device. Let's start with the communication peripherals that can weight the device from stop mode. Firstly, the USARTs. The block diagram for the USART shows some new features compared to the existing USARTs in the STM32 family. We have the wake-up unit to weight the device from stop mode. We have the ability to load the data register as soon as the previous byte has started transmission from the shift registers. The peripheral can now be clocked from a new source, LSE, low speed external as well as the HSI and the RX and TX pins can be swapped. The features of the USARTs are fully flexible just like all other STM32s with the respect to the stop, parity and data bits. All the different modes are still supported with the inclusion of Modbus. And we have now added an auto board rate detection feature. Wake-up from stop is only supported if the USART clock is set to the HSI or LSE as the CIS clock and the P clock are stopped during stop mode. To achieve the wake-up from stop, a set procedure is required as shown before the stop command is executed. An additional deviation for the USART also needs to be taken into account when resuming from stop mode. The auto board rate detection is used to gather the board rate prescalar register settings from an incoming character. Firstly, you have to specify which pattern type you are using, then enable the system and wait for the first character. The operation can be triggered again if required by clearing the ABRF flag. In synchronous mode, the USART can be used to control bidirectional full-duplex synchronous serial communications in master mode. The USART transmitter works exactly like in asynchronous mode, but the S clock is synchronized with the TX according to the CPOL and CPHA settings. The USART supports single wire half-duplex mode. The TX pin is always released when no data is transmitted. Thus, it acts as a standard IO in idle or in reception. It means that the IO must be configured so that TX is configured as alternate function open drain with an external pull-up. In smart card mode, the smart card protocol is half-duplex. S clock is provided to the card for the card internal operation. The bidirectional line is still asynchronous. Urder mode is a half-duplex communications protocol. The SIR transmit encoder modulates the non-return-to-zero transmit bitstream output from the USART. In low power mode, the pulse width is not maintained at 3 over 16 of the period. Generally, this value is 1.8 432 MHz. A low power mode programmable divisor divides the system clock to achieve this value. The USART also supports RS482 and RS422 by use of the divider enable bit. The second communication peripheral to weight the device from stop mode is the I2C. Looking at the block diagram of the I2C peripheral, the main change to the peripheral is the addition of the wake-up block. This block is only present in I2C1 for variants that have more than one cell. We have also added an independent clock source to the I2C cell so that frequency changes on the APB have no impact on the peripheral. The wake-up from stop mode in the I2C is on address match. Just like the USART, the clock source for the peripheral will have to be HSI and not system clock. When a start is detected by the I2C in stop mode, the HSI is automatically enabled. If the address matches, the MCU wake-up interrupt is generated. If the address does not match, HSI is switched off and the MCU remains in stop mode. Clock stretching must be enabled beforehand for this to work correctly to cover the start-up time of the HSI. We have added a new feature to the master mode called AutoEnd. This feature can automatically send the stop condition after the transfer of all bytes without any software intervention. An example of the Control Register 2 settings is shown using this feature. Let's now take a look at the ADC peripheral that has new features for low-power operation. The block diagram for the ADC is the same as most STM32s. We have up to 19 channels going to the analog MUX, up to 16 channels depending on the package, and three internal channels from the temperature sensor, the internal VREF, and the VLCD power supply pin. Multiple trigger events can be configured to start the ADC, including an external line, and the sampling time for each channel can be configured independently. Again like the USART and the I2C, we have connected the HSI at 16 MHz directly to the ADC peripheral. Guaranteeing maximum speed operation when the device core and the peripheral bus are configured at a lower speed. The Auto Off mode has the ability to switch off the ADC and the HSI when it has completed its conversion. Due to the clock circuitry in the ADC, very low-frequency conversions can be made reducing the overall ADC consumption as shown. You also have the ability to reduce the resolution of the answer which will result in a faster conversion time and subsequent lower power consumption. Auto delayed conversion is a mechanism to slow the ADC down to match the speed of the rest of the system. This will remove all possible overrun issues where the next conversion is completed before the data register has been emptied. Auto off mode is the true power saving mode if the trigger events from the application are infrequent as it can turn off the ADC and the HSI when not needed. Used in conjunction with auto delay, the system can be optimized to provide the readings when triggered and when the core requires them. The oversampling unit offloads the CPU of data preprocessing to allow you to perform in hardware averaging, data rate reduction, signal to noise ratio improvement and basic filtering with increased data width up to 16 bits. If we look at an example of what the STM32L0 oversampler does in hardware, we have an accumulated answer of 19 bits. We shift this by 4 to provide a 15 bit result in the 16 bit data register. Thank you for listening to this section.